31.3.18.3 Interrupt Enable Set Register
Symbol | Description | Symbol | Description | Symbol | Description |
---|---|---|---|---|---|
R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
K | Write to clear | S | Software settable bit | — | — |
Name: | INTENSET |
Offset: | 0x000C |
Reset: | 0x00000000 |
Property: | PAC Write-Protection |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
FLTCAP | |||||||||
Access | R/W | ||||||||
Reset | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
CRCERR | CRCDONE | ||||||||
Access | R/W | R/W | |||||||
Reset | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
DERR | SERR | ||||||||
Access | R/W | R/W | |||||||
Reset | 0 | 0 |
Bit 16 – FLTCAP ECC Fault Capture Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a 1 to this bit will enable the ECC Fault Capture as an interrupt request.
Reading this bit returns whether this interrupt is enabled (=1 > enabled).
Bit 9 – CRCERR CRC Error Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a 1 to this bit will enable the CRC Error as an interrupt request.
Reading this bit returns whether this interrupt is enabled (=1 > enabled).
Bit 8 – CRCDONE CRC Calculation Done Interrupt Enable Bit
Writing a '0' to this bit has no effect.
Writing a 1 to this bit will enable the CRC Calculation Done as an interrupt request.
Reading this bit returns whether this interrupt is enabled (=1 > enabled).
Bit 1 – DERR ECC Double Error Detected Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a 1 to this bit will enable the ECC Double Error Detected as an interrupt request.
Reading this bit returns whether this interrupt is enabled (=1 > enabled).
Bit 0 – SERR Single Error Corrected Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a 1 to this bit will enable the Flash SEC as an interrupt request.
Reading this bit returns whether this interrupt is enabled (=1 > enabled).