31.3.18.5 NVM Status Register
Symbol | Description | Symbol | Description | Symbol | Description |
---|---|---|---|---|---|
R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
K | Write to clear | S | Software settable bit | — | — |
Name: | STATUS |
Offset: | 0x0014 |
Reset: | 0x00000000 |
Property: | PAC Write Protection |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
Access | |||||||||
Reset |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
TEMP | PRM | ||||||||
Access | R | R | |||||||
Reset | 0 | 0 |
Bit 1 – TEMP NVM Operating Temperature Read Mode Status
Value | Description |
---|---|
0 | Flash is configured for High Temperature, High Latency reads |
1 | Flash is configured for Standard Temp, Low Latency reads |
Bit 0 – PRM NVM Power Reduction Mode Status
Value | Description |
---|---|
0 | Flash is Ready (for read or NVMOP) |
1 | Flash is Powered Down and wakes on first access (read or NVMOP) |