31.3.18.7 ECC Control Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | ECCCTRL |
| Offset: | 0x001C |
| Reset: | 0x00000040 |
| Property: | PAC Write Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SECCNT[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ECCUNLCK | ECCCTRL[1:0] | ||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 1 | 0 | 0 | ||||||
Bits 15:8 – SECCNT[7:0] Flash SEC Count
SECCNT is the start value of an internal counter that decrements by 1 for each panel reporting an SEC event occurs (including ECC CTL[2:0] bit if in Dynamic ECC Mode). The SECCNT counter stops decrementing at zero. If an SEC error occurs when the SECCNT counter is zero, the INTFLAG.SERR flag bit is set.
Note: This field counts all SEC errors and is not limited to SEC errors on unique
addresses.
Bit 6 – ECCUNLCK NVM ECC Mode Control Unlock
Note: This field can only be modified when ECCUNLCK=1.
The read value dictates the unlock state:
| Value | Description |
|---|---|
| 0 | ECCUNLCK and ECCCTL[1:0] cannot be written |
| 1 | ECCUNLCK and ECCCTL[1:0] can be written |
Bits 5:4 – ECCCTRL[1:0] NVM ECC Mode Control
Restricts one or more NVMOPs:
| Value | Description |
|---|---|
| 11 | Dynamic Writes with No Error Check Reads |
| 10 | Dynamic Writes with SEC Reads but no DED/Parity Bus Error |
| 01 | Dynamic Writes with Dynamic Reads |
| 00 | ECC Writes with ECC Reads (NVMOP = Single Program Operation disabled) |