15.6.5 AHB Client
Bus Interrupt Flag Status and Clear
This flag is set when an access error is
detected by the CLIENT n, and will generate an interrupt request if INTENCLR/SET.ERR is
'1'.
Writing a '0' to this bit has no
effect.
Writing a '1' to this bit will clear the
corresponding INTFLAGAHB interrupt flag.
Table 15-6. Register Bit Attribute
Legend
Symbol
Description
Symbol
Description
Symbol
Description
R
Readable bit
HC
Cleared by Hardware
(Grey cell)
Unimplemented
W
Writable bit
HS
Set by Hardware
X
Bit is unknown at Reset
K
Write to clear
S
Software settable bit
—
—
Name:
INTFLAGAHB
Offset:
0x10
Reset:
0x00000000
Property:
-
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
Access
Reset
Bit
15
14
13
12
11
10
9
8
HSUSB1
HSUSB0
SQI1
SQI0
BROMC
Access
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
Access
Reset
Bits 11, 12 – HSUSB High-Speed Universal Bus
See Note 2 above.
Bits 9, 10 – SQI Serial Quad Interface
See Note 2 above.
Bit 8 – BROMC Boot ROM
Controller
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
