15.6.7 Peripheral Interrupt Flag Status and Clear B

Note: Subsequent to an interrupt flag being cleared, the flag must be read back to verify the clear before exiting the ISR. Failure to do this can result in duplicate interrupts.

This flag is set when a Peripheral Access Error occurs while accessing the peripheral associated with the respective INTFLAGB bit. An interrupt request is generated if INTENCLR/SET.ERR is '1'.

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the corresponding INTFLAGB interrupt flag.

Table 15-8. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit——
Name: INTFLAGB
Offset: 0x18
Reset: 0x00000000
Property: -

Bit 3130292827262524 
     TRNGSQI1SQI0GMAC 
Access R/W/HSR/W/HSR/W/HSR/W/HS 
Reset 0000 
Bit 2322212019181716 
   CAN5CAN4CAN3CAN2CAN1CAN0 
Access R/W/HSR/W/HSR/W/HSR/W/HSR/W/HSR/W/HS 
Reset 000000 
Bit 15141312111098 
 SPI_IXS1SPI_IXS0PTCACADCTCC9TCC8TCC7 
Access R/W/HSR/W/HSR/W/HSR/W/HSR/W/HSR/W/HSR/W/HSR/W/HS 
Reset 00000000 
Bit 76543210 
 TCC6TCC5TCC4TCC3TCC2TCC1TCC0SERCOM9 
Access R/W/HSR/W/HSR/W/HSR/W/HSR/W/HSR/W/HSR/W/HSR/W/HS 
Reset 00000000 

Bit 27 – TRNG True Random Number Generator

Bits 25, 26 – SQIx Serial Quad Interface x = 0,1

See Note 2.

Bit 24 – GMAC Gigabit Media Access Controller

Bits 16, 17, 18, 19, 20, 21 – CANx Controller Area Network, x = 0,1,..5

For CAN4 and CAN5 see Note 2.

For CAN2 and CAN3 see Note 1.

Bits 14, 15 – SPI_IXS Serial Peripheral Interface

Bit 13 – PTC Peripheral Touch Interface

Bit 12 – AC Analog Comparator

Bit 11 – ADC Analog-to-Digital Converter

Bits 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 – TCCx Timer Counter Controller, x = 0,1,...9

Bit 0 – SERCOM9 Serial Communications

See Note 3.