15.6.6 Peripheral Interrupt Flag Status and Clear A
Note: Subsequent to an interrupt flag being cleared, the flag must be read back to verify
the clear before exiting the ISR. Failure to do this can result in duplicate interrupts.
This flag is set when a Peripheral Access Error occurs while accessing the peripheral associated with the respective INTFLAGA bit. An interrupt request is generated if INTENCLR/SET.ERR is one.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the corresponding INTFLAGA interrupt flag.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | INTFLAGA |
| Offset: | 0x14 |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| SERCOM8 | SERCOM7 | SERCOM6 | SERCOM5 | SERCOM4 | SERCOM3 | SERCOM2 | SERCOM1 | ||
| Access | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| SERCOM0 | EVSYS | BROMC | DMAC | PORT | TRAM | MCRAMC-APB | |||
| Access | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DRMTCM | PAC | EIC | RTC | WDT | FREQM | MCLK | GCLK | ||
| Access | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| OSC32KCTRL | OSCCTRL | RSTC | SUPC | PM | FCR-APB | FCW | DSU | ||
| Access | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | R/W/HS | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 23, 24, 25, 26, 27, 28, 29, 30, 31 – SERCOMx Interrupt Flag for SERCOMx, x=0,1,...8
For SERCOM8 see Note 3.
For SERCOM6, see note 2.
For SERCOM5 and SERCOM4 see Note 1.