1.1.1.3 CoreSPI_0 (IAP Initiator)

The CoreSPI IP is used to program the external SPI Flash using the Mi-V processor. This IP interfaces the fabric logic to the external SPI Flash, which is connected to the system controller.

  • APB Data Width: Select 32 as APB data width in the design. The default value is 8.
  • SPI Configuration
    • Mode: Motorola Mode (default) as the target SPI slave supports Motorola Mode. Mode 3 is selected under Motorola configuration.
    • Frame Size: 8
    • FIFO Depth: 32

      To store maximum frames(TX and RX) in FIFO.

    • Clock Rate: 16
  • Motorola Configuration
    • Mode: Mode 3
    • Keep SSEL Active: Enabled

      To keep the slave peripheral active between back to back data transfers.

SPI Clock = System Clock/2x(16+1).

The following figure shows the CoreSPI_0 configuration.
Figure 1-6. CoreSPI Configuration