1.1.1.2 CoreGPIO_0 (IAP Initiator)
The CoreGPIO_0 IP controls the on-board LEDs using GPIOs. It is connected to the Mi-V soft processor as an APB slave. The configuration settings of CoreGPIO_0 are as follows:
- Global Configuration
- APB Data
Width: 32
The design uses 32-bit data width for APB read and write data.
- Number of
I/Os: 1
The design controls one on-board LEDs for output.
- Single-bit interrupt port: Disabled
- Output enable: External
- APB Data
Width: 32
- The following list shows the
sub-options under I/O Bit 0.
- Output on Reset: 0
- Fixed Config: Yes
- I/O Type: Output
- Interrupt Type:
Disabled
When I/O states change, no interrupt is required for the application.