1.1.1.4 CoreAPB3_0 (IAP Initiator)

The CoreAPB3 IP connects the peripherals, PF_SYSTEM_SERVICES, CoreSPI, and CoreGPIO as slaves to the Mi-V soft processor. This IP is configured as follows:
  • APB Master Data Bus Width: 32-bit

    The design uses 32-bit data width for APB read and write data.

  • Number of address bits driven by master: 16
  • Position in slave address of upper 4 bits of master address: [27:24] (Ignored if master address width ≥ 32-bits)
  • Indirect Addressing: Not in use
  • Enabled APB Slave Slots: Slot 0, Slot 1, Slot 2, Slot 3, Slot 4, Slot 5, Slot 6, and Slot 7.
Figure 1-7. CoreAPB3 Configuration (IAP Initiator)
CoreAPB3_0 block interacts with Mi-V and has the following slave interfaces:
  • APB IF UART: (0x6000_0000 to 0x6000_0FFF).

    The APB interface is used by the firmware to get the number of transactions and the last burst size information from the user interface. A dedicated register is used to store the current packet number for the user interface.

  • APB_IF_CORE10GMAC: 0x6000_6000 to 0x6000_6FFF
  • APB_IF_ LSBDATA: 0x6000_4000 to 0x6000_4FFF

    Firmware writes the LSb part of the SPI image to the fabric.

  • APB_IF_ MSBDATA: 0x6000_5000 to 0x6000_5FFF

    Firmware writes the MSb part of the SPI image to the fabric.

  • APB_IF_SS : 0x6000_2000 to 0x6000_2FFF

    This APB interface sends commands to the Core system services.

  • APB_IF_SPI: 0x6000_3000 to 0x6000_3FFF

    This APB interface sends commands and receives data from the external SPI Flash via system controller’s PF_SPI and CoreSPI.