1.5.3 Transmit Lane Alignment

Applications like Serial RapidIO, XAUI, DisplayPort, Interlaken, and JESD204B need transmit alignment across multiple lanes. Transmit lane alignment depends on the number of lanes, total skew, fabric clock frequency relative to the line rate, and number of TX PLLs. The method of alignment involves launching a reset from the shared PLL to each TX lane after the PLLs are locked.

The transceiver PMA quad supports transmit lane alignment for upto four lanes using the following
quad-based reset methods:

• Q#_TxPLL_SSC PLLs and its four lanes (quad) as shown in Figure   1.
• Q#_TxPLL[1:0] and two lanes each from the adjacent quads as shown Figure   2.

The transmit clock for each transceiver lane can be driven by an external or a quad PLL. The reset for the TX lanes is based on the PLL selected. This reset is connected within the transceiver block to travel with the transmit clock. All of the TX lanes for a given TX clock are reset by asserting the internally connected signal TX PLL CLKRESET. To ensure a proper reset, alignment circuitry stops the Tx clock for four clock cycles. With this quad-based reset method, very low skew is achieved. In this scenario, all lanes are within the same QUAD using the same TXPLL. The TXPLL initially align the lanes internally with PLL lock. This occurs prior to the assertion of the PLL_LOCK output pin of the TXPLL. Any subsequent LANE#_PMA_ARSTN assertions will reset the post-dividers for the lane, which can cause a misalignment after the initial alignment that was completed by the CLK_RESET from the TXPLL.

The reinitialization of this lock and alignment mechanism can also be initiated through DRI register control, depending on TXPLL type. Register toggling (1=>0=>1) after initial power-up of PMA_CMN/TXPLL_CTRL/TXPLL_CLKRESET or EXTPLL/EXTPLL_CTRL/EXTPLL_CLKRESET is required. This reset operation requires PMA_CMN/TXPLL_CTRL/TXPLL_CLKRESETEN or EXTPLL/EXTPLL_CTRL/EXTPLL_CLKRESETEN = 1. This action disrupts the TxPLL and re-align the Tx lanes.

Libero SoC software includes support to automatically perform Tx Lane Alignment at start-up. The option is included in the TX PLL configurator to enable or disable (by default, it is disabled) Tx Lane alignment. Enabling this feature automatically generates the initializing instructions to perform alignment after XCVR_INIT_DONE is asserted from the PF_INIT_MONITOR. The Tx Lane Alignment option can be enabled only when Tx PLL is configured in Normal mode. PCIe lanes do not require Tx lane alignment, and it is limited to XCVR lanes configured in any other PCS mode.

In the following scenarios, the quad based reset of TX lanes cannot be used:

• When one transmit clock is used for multiple lanes that do not belong to the same quad. In this scenario, per lane reset of TX lanes must be used because the reset operation on one lane does not affect the other lanes.
• When an arbitrary number of lanes more than four (5 to 8) need the transmit alignment.

In these scenarios, the transceiver uses two PLLs with the same reference clock and a separate fabric logic for reset of the TX lanes as shown in the following figure.

The fabric reset logic per lane is provided by asserting the LANE#_PMA_ARST_N signal (where # represents the lane to be reset). The RESETSEREN# register must be set to reset each lane. To achieve proper skew alignment, the rising and falling edges of the RESETSER# signal must arrive at the transceiver PMA lane pins within two high-speed bit clocks. This can be implemented by a known low-skew internal clock signal using the global or local FPGA routing clocks to Flip-Flop inside the PCS. Any arbitrary low-skew clock can be used as a reference clock to the transceiver Tx PLLs. The Tx_Align pulse needs to be asserted for 16 clock cycles after the PLLs are locked and transmit lanes are programmed with the same post-PLL divide factors. If this requirement is met, all of the TX lanes used for the given transceiver port are aligned within 2-bit clock user interfaces.