1.5.1 Transmit PLL

Two variations of the transmit PLLs embedded within the transceiver lanes are available based on protocol requirements. Both TxPLLs use ring VCO-based PLLs. Using a combination of TxPLL ranges and post-dividers produce frequencies across the entire supported range of the device. The transmit PLLs include one type with spread-spectrum (SSCG) generation modulation capabilities (TXPLL_SSC) and another type without SSCG capabilities (TxPLL). Both types of transmit PLLs use the same half-rate, fractional-N type (Frac-N) architecture design, thereby relaxing the speed requirements of the phase detector and frequency dividers. This consequently expands the VCO tuning range and enhances the phase noise performance while having a significant impact on the total power. The transmit PLL phase detector provides a valid output while driving a full-rate random data stream on both edges using the half-rate clock. All transmit PLLs support a jitter-attenuator option. The jitter attenuator is used to track the data rate of any noisy reference clock with a clean input reference clock to provide a 0 ppm offset from the noisy reference clock while providing a jitter-cleaned output.

Each transceiver lane can select a transmit clock from the transmit PLLs that are close enough to drive their half rate clock (Figure   1). The PLL uses the input reference clock to generate a serial bit clock (at half the rate). The transmit PLL detects and signals a loss of lock in the event that the reference clock stops toggling or when the reference clock transitions to an incorrect frequency.

There are also instances that include additional transmit PLLs, which can be used by the local transceiver quad and in a subset of lanes of adjacent quads.

The output frequency of each transmit PLL is derived automatically from the reference clock frequency and the settings for the PLL multipliers. Each transmit lane can then divide this base transmit PLL rate per lane using the post-divider by 1, 2, 4, 8, or 11. The resulting frequency is half the bit rate based on the transmit half-rate architecture. For example, a 2.5 GHz clock is used for a 5 Gbps transmit transceiver line rate. The programmable multipliers are defined and programmed by the Libero transceiver interface configurator as per the desired protocol.

In addition, the transmit PLL can also provide the system clock for the FPGA logic.

Two different types of transmit PLLs can be used with the transceiver based on half-rate architecture. Both PLL types have identical analog portions with only digital logic differences, therefore each PLL type has identical performance.

Q#_TXPLL_SSC: This PLL operates in the 1.6 GHz – 6.4 GHz frequency range and can provide a transmit bit clock to a transceiver quad. The TxPLL_SSC supports jitter attenuation for loop-time applications. Unique to this PLL is the spread-spectrum clocking (SSC) generation support, which can generate a saw-tooth clock with various options.

For each quad, there is one TxPLL_SSC that can only be used by lanes within that quad.

Q#_TXPLLn: There are two of these PLLs within the transceiver quad location, TxPLL0 and TxPLL1. This type of PLL also supports the full 1.6 GHz – 6.4 GHz frequency range and can drive the transmit bit clock pair of adjacent transmit lanes both above and below the PLL. This PLL also supports jitter attenuation, but does not provide SSC support. There are also transmit PLLs, which can be used by the local transceiver quad and in a subset of lanes of adjacent quads. See Figure   3 and Figure   4 for more information about PolarFire FPGA TxPLL sharing. See Figure   1 for more information about PolarFire SoC FPGA TxPLL sharing.

The jitter attenuation feature uses digital filtering within the transmit PLL to remove the unwanted noise of a reference clock across a wide frequency band. The low-jitter output is sent to an oscillator that is numerically controlled to adjust the phase and frequency relationships to achieve a 0 ppm offset from the original noisy reference clock.