1.5.4 Transceiver Clocks

The transceiver transmitters have high-performance bit clocks running at half the line rate of the fastest transmit lane driven by the clock. The transmit PLLs generate these clocks based on a transmit reference clock, with the configuration set in the Libero design software.

Within each lane, the transmit bit-rate clock (Figure   1) is divided by 1 (full rate), 2, 4, 8, or 11 to set the transmit rate of a given lane. The resulting clock is further divided by 8, 10, 16, 20, 32, 40, 64, and 80 to generate a parallel transmit word clock to the fabric.

The transceiver receivers have their own per-lane receive PLL built into the CDR to generate a per-lane receive clock supporting asynchronous data in that lane. Generally, the CDR is used in lock-to-data mode. The receive CDR PLL initially spins up to approximate the correct frequency to lock to the incoming data by first locking to an input receive reference clock that is near the incoming data rate. Once that is achieved, it then switches to clock recovery mode where it locks to the incoming data and then extracts the clock from the incoming data (which is also a half-rate bit clock running at half the speed of the received data rate). Lock-to-reference is also available for customized protocols. The CDR PLL locks to the local input reference clock and spins to the desired frequency without performing phase compensation or clock recovery functions. These applications pass the data directly to fabric where it can be used for custom over-sampling and synchronizing processing.

The per-lane CDR extracts a clock from the incoming data stream and then generates a receive parallel word clock that is divided by 8, 10, 16, 20, 32, 40, 64, or 80 from the bit rate of the given lane.