1.3.4 PIPE Interface Compliance Exceptions

The PIPE Interface complies with Intel's Specification version 4.0 with the following exceptions.

  • P1 to P0 power-state, PhyStatus pulse response is approximately 30 microseconds delayed from the request to enter P0. The long delay is caused by waiting for the Rx PLL to spin-up and stabilize. The P0-entry is observed externally as a long delay before sending training patterns. The training pattern delay is a fatal protocol error.
  • PCI-Express receiver detection has the following issues when used with soft PIPE interface.
    • A receiver detection returning a Receiver-Not-Present status does so with an oscillating PhyStatus pulse train. MAC-side LTSSM logic must ignore all but the first PhyStatus pulse of the oscillation.
    • A subsequent receiver detection operation N, begins a receiver detect, but immediately returns the status of detection N-1 through PhyStatus and RxStatus when N > 0. The very first receiver detection (N = 0) waits until the conclusion of the receiver detect activity and returns its status through PhyStatus and RxStatus.

The following figure shows how PIPE interface signals behave when the first detection finds no connected receiver. The response time in simulation is fixed for a given reference clock frequency due to the means of modeling the XCVR. The XCVR model has a fixed reflection time of the common-mode voltage step. In real silicon, the reflection time depends upon the termination network, and this also determines when PIPE PhyStatus pulse occurs.

Figure 1-23. Initial Receiver Detection Response For Receiver-Not-Present

The following figure shows how the soft PIPE interface signals behave when the first detection finds a connected receiver. The difference between receiver presence and absence is the value of RxStatus in simulation, but in real silicon, the delay to the PhyStatus pulse can be different. In real silicon, the Receiver-Not-Present response occurs earlier than a Receiver-Present response.

Figure 1-24. Initial Receiver Detection For Receiver-Present

The following figure shows how PIPE interface responds to a successive receiver detection when the prior detection result is Receiver-Not-Present.

Figure 1-25. Subsequent Receiver Detection Where Prior Status Was Receiver-Not-Present