1.3.3 PIPE
(Ask a Question)The transceiver PMA interface to PCIe is based on a standard PIPE interface logic. It provides a standard interface between the PMA lane and the higher link-level of the PHY. The logic handles the following functions:
- 8b10b encoding/decoding logic.
- Lane polarity requirements.
- Elastic FIFO and SKP character logic.
- Hot-plug insertion logic.
- PMA controls required by PCIe standard.
- PCIe detection of remote receiver, power state change, and so on. Provides translation of MACs LTSSM states into PMA power states.
The PIPE interface is used by the embedded PCIESS or can be used with a soft PCIe IP in the FPGA fabric. The embedded PCIESS is accessed through a dedicated interface to the PIPE interface mode, which ties the PCIESS to the PIPE without additional fabric logic. All PHY interface signals are synchronous to the PIPE CLOCK. The PIPE PCS is used as the interconnection between either the embedded PCIe block or used with a fabric-based soft-IP connected to the transceiver PMA. The port list differs slightly based on whether the PIPE interface is configured in PCIe mode. See the PHY Interface for the PCI Express.
| Port Name | Direction | Clock | Description |
|---|---|---|---|
| LANE#_CDR_REF_CLK_#/LANE#_CDR_REF_CLK_FAB | Input | — | Reference clock to lane CDR. Can be sourced from either FPGA clock or from a XCVR_#[A,B,C]REFCLK_P/N pin. |
| LANE#_REF_CLK | Input | — | This port is exposed to user with
Half-Duplex option. LANE#_REF_CLK must be connected by the user to a
stable clock with same clock frequency as Recovered clock such as the
local clock. Note: LANE#_REF_CLK can be provided by
a separate PLL or CCC, however the LANE#_REF_CLK frequency must be
within ± 300 ppm with respect to LANE#_RX_CLK_R. |
| LANE#_TX_PLL_REF_CLK_# | Input | — | Input clock from TX_PLL REF_CLK_TO_LANE output pin. Included in CLKS_FROM_TXPLL_# BIF (bus interface). |
| LANE#_TX_PLL_LOCK_# | Input | — | Input lock status from TX_PLL LOCK output pin. Included in CLKS_FROM_TXPLL_# BIF (bus interface). |
| LANE#_TX_BIT_CLK_# | Input | — | Clock from BIT_CLK of the XCVR TXPLL. Included in CLKS_FROM_TXPLL_# BIF (bus interface). |
| LANE#_TX_DATA[39:0] | Input | — | Parallel data bus to the PCS from the
fabric. The PF_XCVR send/receive order is low to high byte. When the hard PCIESS is used, received data is always 32 bits wide. The upper bits [39:32] are ignored. When the soft PCIe IP design is used, then TXDATA is 40 bits wide; otherwise, it is 32 bits wide (the upper byte is ignored). |
| LANE#_TXDATAK[3:0] | Input | TX_CLK_[R:G] | Indicates the type of characters on the TXDATA bus. A 0 indicates a data character, while 1 indicates a control character. If the soft PCIe IP is used, this signal is ignored. |
| LANE#_TXDETECTRX_LOOPBACK | Input | TX_CLK_[R:G] | High instructs the PHY to begin the receive detect process or external loopback as described in the PCI Express specification. As with many PIPE signals, the meaning of this signal depends on which power state the PHY is in. When in P1 state, this signal informs the PHY to perform a receive detect, but when in P0 state, this signal informs the device to go into loopback mode. |
| TXCOMPLIANCE | Input | TX_CLK_[R:G] | When asserted, this ordinarily forces the currently running disparity to negative. As the name implies, this is useful in conjunction with the transmission of the compliance pattern to generate test data. It is also used in a multi-lane implementation to turn off any unused lanes, for example, when a ×4 link must operate as a ×1. When both TXCOMPLIANCE and TXELECIDLE are asserted, the affected lane turns off to conserve as much power as possible. |
| POWERDOWN[1:0] | Input | TX_CLK_[R:G] | These inputs place the transceiver into
one of four power states: P0: normal operational mode. P0s: PCLK remains on, but the receiver conserves power; entered when the receiver detects electrical idle. Corresponds to link state L0s. P1: PCLK remains on; both the receiver and transmitter are in electrical idle. Corresponds to link state L1. P2: PCLK is off. The PHY must minimize power consumption as it must operate within the VAUX limits. Corresponds to link state L2. See the PHY Interface for the PCI Express for more details on PHY power management. |
| PCIE_RATE | Input | TX_CLK_[R:G] | Controls the link signaling rate.
In
PCIe mode: 0: Gen1 (2.5 Gbps) 1: Gen2 (5.0 Gbps) |
| TXMARGIN[2:0] | Input | TX_CLK_[R:G] | Selects transmitter voltage levels: 000: TxMargin value 0. Normal operating range 001: TxMargin value 1. 800 mV–1200 mV for full swing or 400 mV –700 mV for half swing 010: TxMargin value 2 (required). Vendor defined 011: TxMargin value 3 (required). Vendor defined 100: TxMargin value 4 (required). 200 mV–400 mV for full-swing or 100 mV–200 mV for half-swing 101: TxMargin value 5 (optional). 200 mV–400 mV for full-swing or 100 mV–200 mV for half-swing 110: TxMargin value 6 (optional). 200 mV–400 mV for full swing or 100 mV–200 mV for half-swing 111: TxMargin value 7 (optional). 200 mV–400 mV for full swing or 100 mV–200 mV for half-swing |
| TXDEEMPH | Input | TX_CLK_[R:G] | Selects transmitter de-emphasis: 0: 6 dB de-emphasis at 5 Gbps 1: 3.5 dB de-emphasis at 5 Gbps PIPE implementations that only support 2.5 Gbps signaling rate do not implement this signal. |
| TXSWING | Input | TX_CLK_[R:G] | Controls transmitter voltage swing: 0: Full swing 1: Half swing |
| LANE#_RXPOLARITY | Input | TX_CLK_[R:G] | This active-high signal indicates the PHY to do a polarity inversion on the received data. |
| LANE#_RXSTANDBY | Input | TX_CLK_[R:G] | Used to set the RxStandby state: 0: Active 1: Standby |
| LANE#_TXELECIDLE | Input | TX_CLK_[R:G] | When this signal is asserted high, it forces the transmitter to the electrical idle state regardless of power states. When this signal is de-asserted, valid data from TXDATA and TXDATAK are transmitted in the P0 state. If the PHY is in the P2 state, a beacon must be transmitted when TXELECIDLE is de-asserted. In the P0s and P1 states, TXELECIDLE must be asserted. The use of this signal is also affected by the PHY power state since there are some states in which the transmitter must be electrically idle. See the PHY Interface for the PCI Express for more detail. |
| LANE#_PCS_ARST_N | Input | — | Asynchronous active-low reset for PCS lane. |
| LANE#_PMA_ARST_N | Input | — | Asynchronous active-low reset for PMA lane. |
| LANE#_RXD_N | Input | — | Transceiver receiver differential input. |
| LANE#_RXD_P | Input | — | Transceiver receiver differential input. |
| LANE#_RXELECIDLE | Output | RX_CLK_[R:G] | The PCIe receiver pins detect an electrical idle state on the link. High indicates receiver detection of electrical idle, and low indicates beacon signaling when in P2. |
| LANE#_RXSTANDBYSTATUS | Output | RX_CLK_[R:G] | The PHY uses this signal to indicate
its Rx Standby state. 0: Active 1: Standby |
| LANE#_RX_DATA[39:0] | Output | RX_CLK_[R:G] | Parallel data bus from the PCS to the
fabric. The PF_XCVR send/receive order is low to high byte. When the soft PCIe IP design is used, then RXDATA is 40 bits wide; otherwise, it is 32 bits wide (the upper byte is ignored). |
| LANE#_RXDATAK[3:0] | Output | RX_CLK_[R:G] | The data#/control indicator(s) for the
received symbols on the RXDATA bus: 0: RXDATA contains data 1: RXDATA contains ordered sets If the soft PCIe IP is used, then RXDATAK is ignored. |
| LANE#_RXVALID | Output | RX_CLK_[R:G] | Qualifies the data on RXDATA and RXDATAK. When this signal is asserted, the data on the receive data bus is valid, and the PHY has achieved symbol lock. |
| LANE#_RXSTATUS[2:0] | Output | RX_CLK_[R:G] | Delivers receiver status and error
codes for the received data and receiver detect status from the PHY to
the MAC; for example, SKP symbol added or removed, disparity error,
elastic buffer overflow or underflow, 8b10b decode error, and so on. 0 0 0: Received data OK 0 0 1 1: SKP added 0 1 0 1: SKP removed 0 1 1: Receiver detected 1 0 0: Code error 1 0 1: Elastic buffer overflow 1 1 0: Elastic buffer underflow 1 1 1: Receive disparity error |
| LANE#_RX_BYPASS_DATA | Output | Async | RX_BYPASS_DATA output is a low-speed bypass of the differential receiver that is used for the receive pads. This is a a low-frequency out-of-band debug signal. |
| LANE#_PHYSTATUS | Output | RX_CLK_[R:G] | Signals that the PHY has completed its setup and is ready for data traffic. It is also used to indicate successful transition from power management state, rate change, and receive detection. |
| LANE#_RX_VAL | Output | RX_CLK_[R:G] | LANE#_RX_VAL indicates that the XCVR
data path is initialized. The parallel bus of LANE#_RX_DATA[N:0]
contains actual data recovered from the serial stream when LANE#_RX_VAL
= 1. In PIPIE mode, the Rx PCS logic self-resets when the CDR is not locked. In this mode, LANE#_RX_VAL rises just after LANE#_RX_READY rises. If you want to control Rx PCS reset, hold Rx PCS in reset when LANE#_RX_READY is low and release, when LANE#_RX_READY goes high. Once Rx PCS is released from reset, LANE#_RX_VAL rises to indicate the Rx parallel data is valid. In PIPE mode, the LANE#_RX_VAL is qualified when the CDR locks and the initial comma/word alignment occurs. |
| LANE#_RX_READY | Output | — | Rises when the CDR is phase-locked to
the incoming data transitions and the de-serializer is powered-up. If
there is no incoming data to the CDR then the RX_READY is low. The
primary purpose of this pin is communicating to fabric that the CDR is
locked to serial input data and is producing valid clocking. Note: In a loopback case while looping the local transmitter output to the receiver input, it is necessary to take the Tx out of reset to ensure valid serial transitions, allowing the Rx CDR to lock. The system deadlocks, if the user waits till Rx CDR locks before the Tx is released from reset. |
| LANE#_RX_IDLE | Output | — | Receive electrical-idle detection flag. Asserts asynchronously, but de-asserts synchronously to the RX_CLK_OUT rising edge. |
| LANE#_TX_CLK_STABLE | Output | — | Transmit transceiver/PCS lane ready flag. This flag is 1 when the transmit PLL is locked to the reference clock. |
| LANE#_TX_CLK_[R:G]1 | Output | — | Global or regional transmit clock to fabric. |
| PIPE_CLOCK | Output | — | In PCIe Gen1/Gen2 modes of Soft PIPE PCS setting, there is only one TX_CLK_[R:G] for all the 4 lanes that could be configured in single XCVR configurator instance, that is, LANE0_TX_CLK_[R:G] (renamed as PIPE_CLOCK). This PIPE_CLOCK is commonly used for all the lanes. Internally, both RX_FWF_CLK and TX_FWF_CLK (internal ports on the XCVR macro) of each lane are connected to the PIPE_CLOCK (LANE0_TX_CLK_R/G) through RCLKINT/CLKINT. |
| LANE#_TXD_N | Output | — | Transceiver transmitter differential output. |
| LANE#_TXD_P | Output | — | Transceiver transmitter differential output. |
| (1) In PolarFire FPGA MPF500 devices, RT PolarFire RTPF500 devices, and PolarFire SoC FPGA, the TX_CLK_R and RX_CLK_R pins of XCVR lanes placed in the PCIESS(Q0) and GPSS1(Q1) quads cannot drive I/Os. |