1.3.5 PMA Only

This interface uses the transceiver PMA as a conduit to receive and transmit data to or from the fabric boundary. Serial data is deserialized and sent to the receive FWF before the data is sent to the parallel FPGA fabric bus. Similarly, parallel data from the fabric goes through a transmit FWF prior to entering the parallel interface of the serializer.

The following features are supported in the PMA only mode:

  • Flexible PMA interface width options of [8, 10, 16, 20, 32, 40] bits.
  • Flexible fabric interface width options of [8, 10, 16, 20, 32, 40, 64, 80] bits per clock beat.
  • Fabric control of CDR bit-slip for optional symbol alignment purposes.
  • Fabric control of transmitter electrical-idle.
  • Fabric control override of CDR lock behavior enabling Burst Mode Receiver support.
  • Fabric side interface for transmitter operates at half the frequency of the transmit PMA interface.
  • Fabric side interface for receiver operates at half the frequency of the receiver PMA interface.

The PMA interface bypasses any PCS encoding and decoding logic and is used with customized PCS functionality implemented in the FPGA fabric. The fabric-hosted soft-IP can be customer supplied or 
soft-IP provided through 3rd-party of Microsemi direct cores. The transceiver PMA mode is useful in supporting protocols such as SDI-HD. The PMA Only mode is also used for 1GbE interfaces. The CoreTSE suite of 1GbE IPs contain a soft 8b10b encoder/decoder, which allows the use of either the transceiver or the I/O CDR to implement this standard.

Figure 1-26. PMA-Bus Waveform
Figure 1-27. PMA Only Data Path – 80-bits
Figure 1-28. PMA Only Data Path – Less Than or Equal to 40-bits

The following table lists the port names and description for the PMA mode module.

Table 1-12. PMA Port List
Port NameDirectionClockDescription
LANE#_CDR_REF_CLK_#/LANE#_CDR_REF_CLK_FABInput—Reference clock to lane CDR. Can be sourced from either FPGA clock or from a XCVR_#[A,B,C]REFCLK_P/N pin.
LANE#_REF_CLKInput—This port is exposed to user with Half-Duplex option. LANE#_REF_CLK must be connected by the user to a stable clock with same clock frequency as Recovered clock such as the local clock.
Note: LANE#_REF_CLK can be provided by a separate PLL or CCC, however the LANE#_REF_CLK frequency must be within ± 300 ppm with respect to LANE#_RX_CLK_R.
LANE#_TX_BIT_CLK_[1:0]2Input—Clock from BIT_CLK of the XCVR TxPLL. Included in CLKS_FROM_TXPLL_# BIF (bus interface).
LANE#_TX_PLL_REF_CLK_#Input—Input clock from TX_PLL REF_CLK_TO_LANE output pin. Included in CLKS_FROM_TXPLL_# BIF (bus interface).
LANE#_TX_PLL_LOCK_#Input—Input lock status from TX_PLL LOCK output pin. Included in CLKS_FROM_TXPLL_# BIF (bus interface).
LANE#_TX_DATA[N:0]1InputTX_CLK_[R:G]Transmits data. The PF_XCVR send/receive order is low to high byte. The first serial bit appears in bus bit0. Switching transmission order in PMA mode is accomplished by reversing the bus connections in the fabric.
LANE#_TX_ELEC_IDLEInputAsynchronousTransceiver configurator allows pin to be exposed on component. This input forces XCVR_P/N transmit output pad pair to a common-mode voltage. This can be used for low-frequency out-of-band signaling, or to signal entry into a low-power state to the link partner.
LANE#_TX_BYPASS_DATAInputAsynchronousTransceiver configurator allows pin to be exposed on component. 
When LANE#_TX_BYPASS_DATA=1, the data can be driven into the transmit pads instead of the normal serializer data. The bypass is asynchronous and this signal does not transit through the FWF. This pin must be tied low if exposed to fabric and not used.
LANE#_RX_SLIPInputRX_CLK_[R:G]LANE#_RX_SLIP assertion resets the Rx_FWF causing LANE#_RX_VAL to momentarily deassert(=0). Rising-edge requests that the transceiver lane CDR slip the parallel boundary by one bit. The direction of slip is different for 8b parallel word modes than it is for 10b parallel word modes. See Bit Slip.
LANE#_PCS_ARST_N2Input—Asynchronous active-low reset for the PCS lane.
LANE#_PMA_ARST_N2Input—Asynchronous active-low reset for the PMA lane.
LANE#_RXD_N2Input—Transceiver receiver differential input.
LANE#_RXD_P2Input—Transceiver receiver differential input.
LANE#_RX_DATA[N:0]1OutputRX_CLK_[R:G]Receives data. The PF_XCVR send/receive order is low to high byte. The first serial bit appears in bus bit0.
LANE#_TX_CLK_STABLE2Output—Transmits transceiver/PCS lane ready flag. This flag is 1 when the transmit PLL is locked to the reference clock.
LANE#_RX_VAL2Output—LANE#_RX_VAL indicates that the XCVR data path is initialized. The parallel bus of LANE#_RX_DATA[N:0] contains actual data recovered from the serial stream when LANE#_RX_VAL = 1.

LANE#_RX_VAL is qualified when the XCVR receiver calibration completes, included with the enhanced receiver management completion, and the CDR locks.

LANE#_RX_VAL pulsing low while RX_READY = 1 does not indicate that the clocking is unstable. It means that the LANE#_RX_DATA output is all-zeros temporarily because the Rx datapath is in reset. If that condition does not need to be detected for a specific application, then LANE#_ RX_VAL can be ignored.

Lane#_RX_VAL = 1, indicates the PCS is out of reset, which implies LANE#_RX_READY = 1 because PCS Rx is normally being held in reset while LANE#_RX_READY = 0

LANE#_RX_READY2Output—Lane#_ RX_READY = 1 means the Rx PLL is locked. LANE#_RX_READY rises when the enhanced receiver management and CDR completes a fine lock detection to the incoming data transitions and the de-serializer is powered-up. If there is no incoming data to the CDR then the RX_READY is low. The primary purpose of this pin is communicating to fabric that the CDR is locked to serial input data and is producing valid clocking.

Note: In a loopback case while looping the local transmitter output to the receiver input, it is necessary to take the Tx out of reset to ensure valid serial transitions, allowing the Rx CDR to lock. The system deadlocks, if the user waits till Rx CDR locks before the Tx is released from reset.

LANE#_RX_IDLE2Output—Receives electrical-idle detection flag. LANE#_Rx_IDLE peak detector logic is only valid for a limited minimum density of transitions on the Rx data and not to be used in applications above 5Gbps. Enhanced Receiver Management can provide a reliable mechanism for higher data rates.
LANE#_RX_CLK_[R:G]2Output—Global or regional receive clock to fabric.
LANE#_TX_CLK_[R:G]2, 3Output—Global or regional transmit clock to fabric.
LANE#_TXD_N2Output—Transceiver transmitter differential output.
LANE#_TXD_P2Output—Transceiver transmitter differential output.
(1) N can be 7, 9, 15,19, 31, 39, 63, and 79.

(2) LANE# can be 0, 1, 2, and 3.

(3) In PolarFire FPGA MPF500 devices, RT PolarFire RTPF500 devices, and PolarFire SoC FPGA devices, the TX_CLK_R and RX_CLK_R pins of XCVR lanes placed in the PCIESS(Q0) and GPSS1(Q1) quads cannot drive I/Os.

Important: [R:G] naming is generated based on the use of regional or global resources that are selected with Libero.