17.1.9.1.3 read_verilog
(Ask a Question)Description
Read a Verilog file using Verific.
read_verilog [-lib <libname>] [-mode <mode>] <filename>Arguments
| Parameter | Type | Description |
|---|---|---|
| -lib <libname> | String | Specify the library that contains the modules to be added into the library. |
| -mode <mode> | String | Specify the Verilog standard. Possible values are
verilog_95, verilog_2k, system_verilog_2005,
system_verilog_2009, system_verilog, verilog_ams, verilog_psl,
system_verilog_mfcu. Values are case insensitive.
Default is verilog_2k. |
| filename | String | Verilog file name. |
| Return Type | Description |
|---|---|
| 0 | Command succeeded. |
| 1 | Command failed. There is an error. You can observe the error message in the console. |
List of Errors
| Error Code | Error Message | Description |
|---|---|---|
|
ERR0023 | Parameter—lib is missing value | The lib option is specified without value. |
|
ERR0023 | Parameter—mode is missing value | The mode option is specified without value. |
|
ERR0015 | Unknown mode '<mode>' | The specified verilog mode is unknown. See the list of possible verilog mode in—mode option description. |
|
ERR0023 | Required parameter file name is missing | No verilog file path is provided. |
|
ERR0016 | Failed due to Verific's parser | Syntax error in verilog file. Verific's parser can be observed in the console above the error message. |
|
ERR0012 | set_device is not called | The device information is not specified. Use
set_device command to describe the
device. |
Example
read_verilog -mode system_verilog {component/work/top/top.v}read_verilog -mode system_verilog_mfcu design.v