17.2.2.3 Interpreting Manifest Files

When you open a component manifest file, you see paths to files in your Libero project and pointers on where in the design flow to use them. You might see the following types of files in a manifest file based on the device family you are targeting:

  • HDL source files for all Synthesis and Simulation tools
  • HDL source files for Synopsys SynplifyPro Synthesis tool
  • Stimulus files for all Simulation tools
  • Configuration files to be used for all Simulation tools
  • Firmware files for all Software IDE tools
  • Configuration files to be used for Programming
  • Configuration files to be used for Power Analysis

The following is the Component Manifest (example of a SmartFusion 2 System Builder component).

HDL source files for all Synthesis and Simulation tools:
    D:/Designs/g4proj/component/work/toplevelsd_sb/CCC_0/toplevelsd_sb_CCC_0_FCCC.v
    D:/Designs/g4proj/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_addrdec.v
    D:/Designs/g4proj/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_defaultslavesm.v
    D:/Designs/g4proj/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_slavearbiter.v
    D:/Designs/g4proj/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_masterstage.v
    D:/Designs/g4proj/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_slavestage.v
    D:/Designs/g4proj/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_matrix4x16.v
    D:/Designs/g4proj/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite.v
    D:/Designs/g4proj/component/Actel/DirectCore/CoreConfigP/7.1.100/rtl/vlog/core/coreconfigp.v
    D:/Designs/g4proj/component/Actel/DirectCore/CoreResetP/7.1.100/rtl/vlog/core/coreresetp.v
    D:/Designs/g4proj/component/Actel/DirectCore/CoreResetP/7.1.100/rtl/vlog/core/coreresetp_pcie_hotreset.v
    D:/Designs/g4proj/component/work/toplevelsd_sb/FABDDR_0/toplevelsd_sb_FABDDR_0_FDDRC.v
    D:/Designs/g4proj/component/work/toplevelsd_sb/FABOSC_0/toplevelsd_sb_FABOSC_0_OSC.v
    D:/Designs/g4proj/component/work/toplevelsd_sb/toplevelsd_sb.v
    D:/Designs/g4proj/component/work/toplevelsd_sb_MSS/toplevelsd_sb_MSS.v

HDL source files for Synopsys SynplifyPro Synthesis tool:
    D:/Designs/g4proj/component/work/toplevelsd_sb/FABDDR_0/toplevelsd_sb_FABDDR_0_FDDRC_syn.v
    D:/Designs/g4proj/component/Actel/SgCore/OSC/2.0.101/osc_comps.v
    D:/Designs/g4proj/component/work/toplevelsd_sb_MSS/toplevelsd_sb_MSS_syn.v

Stimulus files for all Simulation tools:
    D:/Designs/g4proj/component/work/toplevelsd_sb/subsystem.bfm
    D:/Designs/g4proj/component/work/toplevelsd_sb_MSS/CM3_compile_bfm.tcl
    D:/Designs/g4proj/component/work/toplevelsd_sb_MSS/user.bfm
    D:/Designs/g4proj/component/work/toplevelsd_sb_MSS/test.bfm
    D:/Designs/g4proj/component/Actel/SmartFusion 2MSS/
MSS/1.1.500/peripheral_init.bfm

Firmware files for all Software IDE tools:
    D:/Designs/g4proj/component/work/toplevelsd_sb/FABDDR_0/sys_config_fddr_define.h
    D:/Designs/g4proj/component/work/toplevelsd_sb_MSS/sys_config_mss_clocks.h
    D:/Designs/g4proj/component/work/toplevelsd_sb_MSS/sys_config_mddr_define.h

Configuration files to be used for all Simulation tools:
    D:/Designs/g4proj/component/work/toplevelsd_sb/FABDDR_0/FDDR_init.bfm
    D:/Designs/g4proj/component/work/toplevelsd_sb_MSS/MDDR_init.bfm

Configuration files to be used for Power Analysis:
    D:/Designs/g4proj/component/work/toplevelsd_sb_MSS/MDDR_init.reg
    D:/Designs/g4proj/component/work/toplevelsd_sb/FABDDR_0/FDDR_init.reg

The following is the Component Manifest (example of a PolarFire core component).

HDL source files for all Synthesis and Simulation tools:
    D:/Designs/manifestex/component/Actel/SgCore/PF_SYSTEM_SERVICES/3.0.100/rtl/vlog/core/CoreSysServices_PF_APBS.v
    D:/Designs/manifestex/component/Actel/SgCore/PF_SYSTEM_SERVICES/3.0.100/rtl/vlog/core/CoreSysServices_PF_Ctrl.v
    D:/Designs/manifestex/component/Actel/SgCore/PF_SYSTEM_SERVICES/3.0.100/rtl/vlog/core/CoreSysServices_PF_ReqArbiter.v
    D:/Designs/manifestex/component/Actel/SgCore/PF_SYSTEM_SERVICES/3.0.100/rtl/vlog/core/CoreSysServices_PF_MBXIF.v
    D:/Designs/manifestex/component/Actel/SgCore/PF_SYSTEM_SERVICES/3.0.100/rtl/vlog/core/CoreSysServices_PF_SSIIF.v
    D:/Designs/manifestex/component/work/PF_SYSTEM_SERVICES_C0/PF_SYSTEM_SERVICES_C0_0/rtl/vlog/core/PF_System_Services.v
    D:/Designs/manifestex/component/work/PF_SYSTEM_SERVICES_C0/PF_SYSTEM_SERVICES_C0.v

Each type of file is a necessary downstream in your design flow. The following sections describe integration of the files from the manifest into your design flow.