17.2.2.1 Component Configuration Using Libero

After selecting the components that must be used from the preceding list, perform the following steps:
  1. Create a new Libero project (Core Configuration and Generation):
    1. Select the Device and Family that you target your final design to.
    2. If you use the SmartFusion 2 MSS, SmartFusion 2, or IGLOO 2 System Builder, make the appropriate selection in theUse Design Flow section of the New Project window.
  2. If you use Smart Fusion 2 or IGLOO 2 System Builder (for IGLOO 2, you must use the System Builder to configure the HPMS, eNVM, MDDR, and FDDR):
    1. Use the System Builder to select your components and configure your system.
    2. Generate your system in the System Builder and promote all its ports to the top level after instantiating in a SmartDesign canvas (select all ports, right-click and choose Promote to Top).
      Tip: You need the port names to connect the rest of your design to the generated system.
    3. Instantiate and configure any CCC or SerDes blocks in the same top-level SmartDesign or in another SmartDesign component. Again, promote any ports to top.
    4. Generate any SmartDesign instances.
    5. Double-click the Simulate tool (Pre-Synthesis) to invoke the simulator. You can exit the simulator once it is invoked—this step generates the simulation files necessary for your project.
      Tip: You must perform this step if you want to simulate your design outside Libero.
    6. Save your project—this is your reference project.
  3. If you do not use the System Builder (SmartFusion 2 only):
    1. If you select the SmartFusion 2 MSS in the Use Design Flow subsection (step 1.b), the SmartFusion 2 MSS Configurator automatically opens. Otherwise, in the Design Flow window, double-click Configure MSS.
      1. Double-click the SmartFusion 2 MSS instance to open its configurator.
      2. Configure the SmartFusion 2 MSS as per your requirements.
        Tip: If you use the eNVM or the MDDR, you must use the SmartFusion 2 MSS to configure it.
      3. Save and generate the SmartFusion 2 MSS component.
        Tip: If you do not use the System Builder, and you have the SmartFusion 2 MSS (using MDDR) or FDDR or SerDes blocks in your design, you must follow the next steps.
    2. Construct the Peripheral Initialization architecture in your final design. For more details, about Peripheral Initialization, see:
    3. Instantiate and configure any FDDR, CCC, or SerDes blocks in the top-level SmartDesign. It is not necessary to connect them to anything else—just promote any ports to top.
    4. Generate all the SmartDesigns built in the preceding steps.
    5. Double-click the Simulate tool (Pre-Synthesis) to invoke the simulator. You can exit the simulator after it is invoked; this step simply generates the simulation files necessary for your project.
      Tip: You must perform this step if you want to simulate your design outside Libero.

      For more information, see 17.2.5 Simulating Your Design.

    6. Save your project—this is your reference project.
  4. If you use the SmartFusion 2, and any of the SmartFusion 2 MSS peripherals (MDDR, FDDR, or SerDes), you must export your firmware project (SoftConsole/IAR/Keil) from this Libero project. For more information, see 17.2.7 Building Your Firmware Project.
  5. If you use the RTG4:
    1. If you want to use the SerDes and the FDDR blocks in your design with built-in Initialization logic, configure and generate the corresponding INIT cores (NPSS_SERDES_IF_INIT, PCIE_SERDES_IF_INIT, and RTG4FDDRC_INIT) from the Libero catalog.
    2. If you want to use the SerDes and the FDDR blocks in your design without built-in Initialization logic, configure and generate the corresponding peripheral cores from the Libero catalog.
      Tip: If you are using SerDes and FDDR blocks in your design, but not their corresponding INIT cores, you must construct the Peripheral Initialization architecture in your final design to initialize the RTG4 SerDes and the FDDR blocks. For further details regarding Peripheral Initialization, see:
    3. Instantiate and configure any FDDR, CCC, OSC, or SerDes blocks in the top level SmartDesign. It is not necessary to connect them to anything else — just promote any ports to top.
    4. If you want to use RTG4 uPROM, add the uPROM block to the top level SmartDesign.
    5. Generate all the SmartDesigns built in the above steps.
    6. Double-click Simulate (Pre-Synthesis) to invoke the simulator. You can exit the simulator after it is invoked; this step only generates the simulation files that are necessary for your project.
      Tip: To generate UPROM.mem file (used for simulating the UPROM contents) from the UPROM.cfg file (generated by the configurator) using a stand-alone executable outside Libero, see 17.2.5 Simulating Your Design. You must perform this step if you want to simulate your design outside of Libero.
    7. Save your project—this is your reference project.
      Tip: You must follow the DRCs for components that you instantiate. For example, if you have multiple SerDes instances in your design, make sure that each SerDes instance is configured to select a different physical SerDes block. Refer to the user guides for the respective component DRCs for details.
  6. If you use the PolarFire device, use one or more of the PolarFire cores mentioned in 17.2.1.3 Custom Flow.
    1. Create a SmartDesign and configure the desired core and instantiate it in the SmartDesign component.
    2. Promote all the pins to top level.
    3. Generate the SmartDesign.
    4. Double-click the Simulate tool (any of the Pre-Synthesis or Post-Synthesis or Post-Layout options) to invoke the simulator. You can exit the simulator after it is invoked. This step generates the simulation files necessary for your project.
      Tip: You must perform this step if you want to simulate your design outside Libero.

      For more information, see 17.2.5 Simulating Your Design.

    5. Save your project—this is your reference project.