25.5.3 Control C
| Name: | CTRLC |
| Offset: | 0x02 |
| Reset: | 0x00 |
| Property: | Double-Buffered |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| WGPULSE[2:0] | WO1POL | WO0POL | WO1EN | WO0EN | |||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bits 6:4 – WGPULSE[2:0] Waveform Generation Pulse Length
| Value | Name | Description |
|---|---|---|
| 0x0 | CLK1 | High pulse is 1 Timer/Counter clock period |
| 0x1 | CLK2 | High pulse is 2 Timer/Counter clock periods |
| 0x2 | CLK4 | High pulse is 4 Timer/Counter clock periods |
| 0x3 | CLK8 | High pulse is 8 Timer/Counter clock periods |
| 0x4 | CLK16 | High pulse is 16 Timer/Counter clock periods |
| 0x5 | CLK32 | High pulse is 32 Timer/Counter clock periods |
| 0x6 | CLK64 | High pulse is 64 Timer/Counter clock periods |
| 0x7 | CLK128 | High pulse is 128 Timer/Counter clock periods |
Bit 3 – WO1POL Waveform Output 1 Polarity
| Value | Description |
|---|---|
| 0 | The waveform output WO1 is set on overflow and cleared on compare match |
| 1 | The waveform output WO1 is cleared on overflow and set on compare match |
Bit 2 – WO0POL Waveform Output 0 Polarity
| Value | Description |
|---|---|
| 0 | The waveform output WO0 is set on overflow and cleared on compare match |
| 1 | The waveform output WO0 is cleared on overflow and set on compare match |
Bit 1 – WO1EN Waveform Output 1 Enable
| Value | Description |
|---|---|
| 0 | The waveform output is disconnected |
| 1 | The waveform output is available on corresponding pin |
Bit 0 – WO0EN Waveform Output 0 Enable
| Value | Description |
|---|---|
| 0 | The waveform output is disconnected |
| 1 | The waveform output is available on corresponding pin |
