25.5.7 Interrupt Flags

Name:	INTFLAGS
Offset:	0x06
Reset:	0x00
Property:	-


Bit	7	6	5	4	3	2	1	0
						CMP1	CMP0	OVF
Access						R/W	R/W	R/W
Reset						0	0	0

Bit 2 – CMP1 Compare 1 Flag

This bit is set when an interrupt occurs. The interrupt conditions depend on the Waveform Generation Mode (WGMODE) bit field in the Control B (TCFn.CTRLB) register.

This bit is cleared by writing a '1' or writing the Compare register.

Bit 1 – CMP0 Compare 0 Flag

This bit is set when an interrupt occurs. The interrupt conditions depend on the Waveform Generation Mode (WGMODE) bit field in the Control B (TCFn.CTRLB) register.

This bit is cleared by writing a '1' or writing the Compare register.

Bit 0 – OVF Overflow Interrupt Flag

This bit is set when an overflow interrupt occurs. The flag is set whenever the timer/counter wraps from MAX to BOTTOM.

Writing a ‘1’ to the bit position clears the bit.