25.5.11 Compare Register

The TCFn.CMP0, TCFn.CMP1, TCFn.CMP2 and TCFn.CMP3 registers represent the 32-bit value TCFn.CMP. Byte 0 [7:0] is accessible at the original offset. Byte 1 [15:8] is accessible at the offset + 0x1. Byte 2 [23:16] is accessible at the offset + 0x2. Byte 3 [31:24] is accessible at the offset + 0x3, but it never contains any data.

A write or read access to byte 2 (offset + 0x2) triggers a new synchronization.

In the 8-bit PWM mode, only TCFn.CMP0 and TCFn.CMP1 are used and accessed as independent registers. TCFn.CMP2 and TCFn.CMP3 do not have any function in this mode.

Name:	CMP
Offset:	0x14
Reset:	0x00
Property:	Double-Buffered


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
	CMP[23:16]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	CMP[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	CMP[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 23:0 – CMP[23:0] Compare Value

This bit field holds the compare, top or increment value.