26.6 Register Summary


Offset	Name	Bit Pos.	7	6	5	4	3	2	1	0
0x00	WRCTRL	7:0	PERID[7:0]
		15:8	PERID[15:8]
		23:16	KEY[7:0]
		31:24
0x04	EVCTRL	7:0								ERREO
0x05 ... 0x07	Reserved
0x08	INTENCLR	7:0								ERR
0x09	INTENSET	7:0								ERR
0x0A ... 0x0F	Reserved
0x10	INTFLAGAHB	7:0	PBBB	PBAB	PFLASH	CFLASH	SRAM3	SRAM2	SRAM1	SRAM0
		15:8					PUKCC	QSPI	PBPICB	PBCB
		23:16
		31:24
0x14	INTFLAGA	7:0	TC2	TC1	TC0	SERCOM1	SERCOM0	EIC	FREQM	PAC
		15:8					TCC2	TCC1	TCC0	TC3
		23:16
		31:24
0x18	INTFLAGB	7:0				RAMECC	EVSYS	DMAC		DSU
		15:8
		23:16
		31:24
0x1C	INTFLAGC	7:0	AC	CCL		SERCOM3	SERCOM2		AES	QSPI
		15:8						TRNG
		23:16
		31:24
0x20 ... 0x33	Reserved
0x34	STATUSA	7:0	TC2	TC1	TC0	SERCOM1	SERCOM0	EIC	FREQM	PAC
		15:8					TCC2	TCC1	TCC0	TC3
		23:16
		31:24
0x38	STATUSB	7:0				RAMECC	EVSYS	DMAC		DSU
		15:8
		23:16
		31:24
0x3C	STATUSC	7:0	AC	CCL		SERCOM3	SERCOM2		AES	QSPI
		15:8						TRNG
		23:16
		31:24