35.15 TWI

Table 35-21. TWI - Timing Characteristics
Symbol	Description	Min.	Typ.	Max.	Unit	Condition
f_SCL	SCL clock frequency	0	—	1000	kHz	Max. frequency requires system clock at 10 MHz
0	—	400	kHz	For V_DD < 2.2V
V_IH	Input high voltage	0.7×V_DD	—	—	V
V_IL	Input low voltage	—	—	0.3×V_DD	V
V_HYS	Hysteresis of Schmitt Trigger inputs	0.1×V_DD		0.4×V_DD	V
V_OL	Output low voltage	—	—	0.2xV_DD	V	I_load = 20 mA, Fast mode+
—	—	0.4V	I_load = 3 mA, Normal mode, V_DD > 2V
—	—	0.2×V_DD	I_load = 3 mA, Normal mode, V_DD ≤ 2V
I_OL	Low level output current	3	—	—	mA	f_SCL ≤ 400 kHz, V_OL = 0.4V
20	—	—	f_SCL ≤ 1 MHz, V_OL = 0.4V
C_B	Capacitive load for each bus line	—	—	400	pF	f_SCL ≤ 100 kHz
—	—	400	f_SCL ≤ 400 kHz
—	—	550	f_SCL ≤1 MHz
t_R	Rise time for both SDA and SCL	—	—	1000	ns	f_SCL ≤ 100 kHz
20	—	300	f_SCL ≤ 400 kHz
—	—	120	f_SCL ≤ 1 MHz
t_OF	Output fall time from V_IHmin to V_ILmax	—	—	250	ns	f_SCL ≤ 100 kHz 10 pF < C_B < 400 pF
20×(V_DD/5.5V)	—	250	f_SCL ≤ 400 kHz 10 pF < C_B < 400 pF
20×(V_DD/5.5V)	—	120	f_SCL ≤ 1 MHz 10 pF < C_B < 400 pF
t_SP	Spikes suppressed by the input filter	0	—	50	ns
I_L	Input current for each I/O pin	—	—	1	µA	0.1×V_DD < V_I < 0.9×V_DD
C_I	Capacitance for each I/O pin	—	—	10	pF
R_P	Value of pull-up resistor	(V_DD-V_OL(max)) /I_OL	—	1000 ns/(0.8473×C_B)	Ω	f_SCL ≤ 100 kHz
—	—	300 ns/(0.8473×C_B)	f_SCL ≤ 400 kHz
—	—	120 ns/(0.8473×C_B)	f_SCL ≤ 1 MHz
t_{HD_STA}	Hold time (repeated) Start condition	4.0	—	—	µs	f_SCL ≤ 100 kHz
0.6	—	—	f_SCL ≤ 400 kHz
0.26	—	—	f_SCL ≤ 1 MHz
—	2.1	—	T_SCL	Start
—	3.1	—	Repeated Start
T_LOW	Low period of SCL Clock	4.7	—	—	µs	f_SCL ≤ 100 kHz
1.3	—	—	f_SCL ≤ 400 kHz
0.5	—	—	f_SCL ≤ 1 MHz
T_HIGH	High period of SCL Clock	4.0	—	—	µs	f_SCL ≤ 100 kHz
0.6	—	—	f_SCL ≤ 400 kHz
0.26	—	—	f_SCL ≤ 1 MHz
t_{SU_STA}	Setup time for a repeated Start condition	4.7	—	—	µs	f_SCL ≤ 100 kHz
0.6	—	—	f_SCL ≤ 400 kHz
0.26	—	—	f_SCL ≤ 1 MHz
—	3	—	T_SCL
t_{HD_DAT}	Data hold time	—	0	—	ns	SDAHOLD[1:0] = `0x0`
30	—	300	SDAHOLD[1:0] = `0x1`
120	—	420	SDAHOLD[1:0] = `0x2`
300	—	900	SDAHOLD[1:0] = `0x3`
t_{SU_DAT}	Data setup time	250	—	—	ns	f_SCL ≤ 100 kHz
100	—	—	f_SCL ≤ 400 kHz
50	—	—	f_SCL ≤ 1 MHz
t_{SU_STO}	Setup time for Stop condition	4	—	—	µs	f_SCL ≤ 100 kHz
0.6	—	—	f_SCL ≤ 400 kHz
0.26	—	—	f_SCL ≤ 1 MHz
—	2	—	T_SCL
t_BUF	Bus free time between a Stop and Start condition	4.7	—	—	µs	f_SCL ≤ 100 kHz
1.3	—	—		f_SCL ≤ 400 kHz
0.5	—	—		f_SCL ≤ 1 MHz
—	2	—	T_SCL
Note: I²C Fm+ is supported only above 2.7V.

f_SCL

SCL clock frequency

0

—

1000

kHz

Max. frequency requires system clock at 10 MHz

0

—

400

kHz

For V_DD < 2.2V

V_IH

Input high voltage

0.7×V_DD

—

V

V_IL

Input low voltage

—

0.3×V_DD

V

V_HYS

Hysteresis of Schmitt Trigger inputs

0.1×V_DD

0.4×V_DD

V

V_OL

Output low voltage

—

0.2xV_DD

V

I_load = 20 mA, Fast mode+

—

0.4V

I_load = 3 mA, Normal mode, V_DD > 2V

—

0.2×V_DD

I_load = 3 mA, Normal mode, V_DD ≤ 2V

I_OL

Low level output current

3

—

mA

f_SCL ≤ 400 kHz, V_OL = 0.4V

20

—

f_SCL ≤ 1 MHz, V_OL = 0.4V

C_B

Capacitive load for each bus line

—

400

pF

f_SCL ≤ 100 kHz

—

400

f_SCL ≤ 400 kHz

—

550

f_SCL ≤1 MHz

t_R

Rise time for both SDA and SCL

—

1000

ns

f_SCL ≤ 100 kHz

20

—

300

f_SCL ≤ 400 kHz

—

120

f_SCL ≤ 1 MHz

t_OF

Output fall time from V_IHmin to V_ILmax

—

250

ns

f_SCL ≤ 100 kHz

10 pF < C_B < 400 pF

20×(V_DD/5.5V)

—

250

f_SCL ≤ 400 kHz

10 pF < C_B < 400 pF

20×(V_DD/5.5V)

—

120

f_SCL ≤ 1 MHz

10 pF < C_B < 400 pF

t_SP

Spikes suppressed by the input filter

0

—

50

ns

I_L

Input current for each I/O pin

—

1

µA

0.1×V_DD < V_I < 0.9×V_DD

C_I

Capacitance for each I/O pin

—

10

pF

R_P

Value of pull-up resistor

(V_DD-V_OL(max)) /I_OL

—

1000 ns/(0.8473×C_B)

Ω

f_SCL ≤ 100 kHz

—

300 ns/(0.8473×C_B)

f_SCL ≤ 400 kHz

—

120 ns/(0.8473×C_B)

f_SCL ≤ 1 MHz

t_{HD_STA}

Hold time (repeated) Start condition

4.0

—

µs

f_SCL ≤ 100 kHz

0.6

—

f_SCL ≤ 400 kHz

0.26

—

f_SCL ≤ 1 MHz

—

2.1

—

T_SCL

Start

—

3.1

—

Repeated Start

T_LOW

Low period of SCL Clock

4.7

—

µs

f_SCL ≤ 100 kHz

1.3

—

f_SCL ≤ 400 kHz

0.5

—

f_SCL ≤ 1 MHz

T_HIGH

High period of SCL Clock

4.0

—

µs

f_SCL ≤ 100 kHz

0.6

—

f_SCL ≤ 400 kHz

0.26

—

f_SCL ≤ 1 MHz

t_{SU_STA}

Setup time for a repeated Start condition

4.7

—

µs

f_SCL ≤ 100 kHz

0.6

—

f_SCL ≤ 400 kHz

0.26

—

f_SCL ≤ 1 MHz

—

3

—

T_SCL

t_{HD_DAT}

Data hold time

—

0

—

ns

SDAHOLD[1:0] = 0x0

30

—

300

SDAHOLD[1:0] = 0x1

120

—

420

SDAHOLD[1:0] = 0x2

300

—

900

SDAHOLD[1:0] = 0x3

t_{SU_DAT}

Data setup time

250

—

ns

f_SCL ≤ 100 kHz

100

—

f_SCL ≤ 400 kHz

50

—

f_SCL ≤ 1 MHz

t_{SU_STO}

Setup time for Stop condition

4

—

µs

f_SCL ≤ 100 kHz

0.6

—

f_SCL ≤ 400 kHz

0.26

—

f_SCL ≤ 1 MHz

—

2

—

T_SCL

t_BUF

Bus free time between a Stop and Start condition

4.7

—

µs

f_SCL ≤ 100 kHz

1.3

—

f_SCL ≤ 400 kHz

0.5

—

f_SCL ≤ 1 MHz

—

2

—

T_SCL

Note: I²C Fm+ is supported only above 2.7V.