35.16 ADC

Table 35-22. ADC Accuracy Specifications
Operating Conditions:
  • VADCREF = 3.0V
  • ADC in 10-bit, single ended conversion mode
  • fCLK_ADC = 1 MHz
SymbolDescriptionMin.Typ. ✝Max.UnitConditions
NRResolution——10bit
EINLIntegral nonlinearity error-1.80.11.8LSb
EDNLDifferential nonlinearity error(1)-10.11LSb
EOFFOffset error02.55LSb
EGAINGain error-51.55LSb
VADCREF *ADC reference voltage 1.024—VDDVfCLK_ADC ≤ 500 kHz
1.8—VDDV
VAINFull-scale rangeGND—VADCREFV
ZAINRecommended impedance of analog voltage source—10—kΩ
RVREFAADC voltage reference ladder impedance(2)—50—kΩ

VDD/10 divider accuracy
(VDDDIV10)

—±10—%Measured with ADC using on-chip internal reference

✝ Data in the “Typ.” column are measured at TA = 25°C and VDD = 3.0V, unless otherwise specified. These parameters are provided for design guidance only and are not tested.

* These parameters are characterized but not tested in production.

Note:
  1. The ADC conversion result never decreases with an increase in the input and has no missing codes.
  2. This is the impedance seen by the VREFA pin when the external reference is selected.
Table 35-23. ADC Conversion Timing Specifications
SymbolDescriptionMin.Typ. ✝Max.UnitConditions
TCLK_ADC *ADC clock period0.5—8μs
tCNVConversion time —11.5TCLK_ADC + 2TCLK_PER—
fADC *Sample rate8—170kspsCLK_PER=24 MHz
tSENSE *Delay for changing MUXPOS to TEMP—40—μs
tADC_INIT *Initialization time—6—μs

✝ Data in the “Typ.” column are measured at TA = 25°C and VDD = 3.0V, unless otherwise specified. These parameters are provided for design guidance only and are not tested.

* These parameters are characterized but not tested in production.