22.5.16 Debug Control

Offset: 0x1E
Reset: 0x00
Property: -

Bit 76543210 
Access R/WR/W 
Reset 00 

Bit 2 – FAULTDET Fault Detection

This bit defines how the peripheral behaves when stopped in Debug Mode.

0 NONE No fault is generated if TCD is stopped in debug mode.
1 FAULT A fault is generated and both trigger flags are set if TCD is halted in debug mode.

Bit 0 – DBGRUN Debug Run

0 The peripheral is halted in break debug mode and ignores events.
1 The peripheral will continue to run in break debug mode when the CPU is halted.