22.5.9 Status
| Name: | STATUS |
| Offset: | 0x0E |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PWMACTB | PWMACTA | CMDRDY | ENRDY | ||||||
| Access | R/W | R/W | R | R | |||||
| Reset | 0 | 0 | 0 | 0 |
Bits 6, 7 – PWMACT PWM Activity on x
This bit is set by hardware each time the output WO1 toggles from 0 to 1 or from 1 to 0.
This status bit must be cleared by software by writing a '1' to it before new PWM activity can be detected.
Bit 1 – CMDRDY Command Ready
This status bit tells when a command is synced to the TCD domain and the system is ready to receive new commands.
The following clears the CMDRDY bit:
- TCD.CTRLE SYNCEOC strobe
- TCD.CTRLE SYNC strobe
- TCD.CTRLE RESTART strobe
- TCD.CTRLE SCAPTUREA Capture A strobe
- TCD.CTRLE SCAPTUREB Capture B strobe
- TCD.CTRLC AUPDATE written to '1' and writing to TCD.CMPBCLRH register
Bit 0 – ENRDY Enable Ready
This status bit tells when the ENABLE value in TCD.CTRLA is synced to the TCD domain, and is ready to be written to again.
The following clears the ENRDY bit:
- Writing to the ENABLE bit in (TCD.CTRLA
- TCD.CTRLE DISEOC strobe
- Going to break in an On-Chip Debugging (OCD) session with and the Debug Run bit (DBGCTRL) in TCD.DBGCTRL is not '1'