1.9 SPI Host Module

The MCP2222 SPI host interface consists of MOSI, MISO, SCK, and CS, which are the data-out, data-in, clock, and chip select signals, respectively. It is responsible for SPI traffic generation. The SPI host interface supports configurable clock speed, SPI mode, and delay between data bytes.

The SPI host is controlled using SPI interface commands.

The SPI host supports the following features:

• Clock frequency: Up to 12 Mbps
• SPI modes: All four modes: 0 to 3
• Up to four chip select outputs for communication with multiple SPI client devices
• Single transfers of up to 65,535 bytes
• Configurable delay from 0 μs to 5000 μs for:
  • Chip-select assertion to the first data byte
  • Delay between data bytes
  • Last data byte to chip-select deassertion

All user data transmitted or received over the SPI bus is exchanged with the USB host through the USB vendor-class interface.