1.1 Bank Locations

PolarFire SoC FPGA I/O are grouped based on I/O voltage standards and I/O capabilities. Each I/O bank has dedicated I/O supplies and ground voltages. Due to these dedicated supplies, only I/O with compatible standards are assigned to the same I/O voltage bank.

The following illustrations show the bank locations for the MPFS460T, MPFS250T, MPFS160T, MPFS095T, and MPFS025T devices with available package combinations.

Figure 1-1. PolarFire SoC FPGA MPFS460T-FCG1152 I/O Bank Locations
Figure 1-2. PolarFire SoC FPGA MPFS250T-FCG1152 I/O Bank Locations
Figure 1-3. PolarFire SoC FPGA MPFS250T/MPFS160T-FCVG784 I/O Bank Locations
Figure 1-4. PolarFire SoC FPGA MPFS095T-FCVG784 I/O Bank Locations
Figure 1-5. PolarFire SoC FPGA MPFS250T-MPFS160T-MPFS095T-MPFS025T-FCVG484 I/O Bank Locations
Figure 1-6. PolarFire SoC FPGA MPFS250T-MPFS160T-FCSG536 I/O Bank Locations
Important: Bank 9 VDDI and VDDAUX power pins are connected to Bank 1 VDDI and VDDAUX power pins, respectively, within the package substrate for pin migration compatibility.
Figure 1-7. PolarFire SoC FPGA MPFS095T-FCSG536 I/O Bank Locations
Figure 1-8. PolarFire SoC FPGA MPFS095T-MPFS025T-FCSG325 I/O Bank Locations
Important: The MPFS095T and MPFS025T in the FCSG325 package do not support fabric DDR3, DDR4, LPDDR3, or LPDDR4 memory interfaces. The MSS-DDR bank allows the MSS DDR controller to use MSS_DDR3, MSS_DDR4, MSS_LPDDR3, or MSS_LPDDR4 interfaces with DQ Width = x16. For more information, see the respective Package Pin Assignment Table on the Microchip website.