11 Revision History

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The revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the most current publication.

Table 11-1. Revision History
Revision	Date	Description
E	05/2025	The following is a summary of the changes made in revision E of this document. Updated all Bank Locations figures and added a note for the MPFS095T and MPFS025T in the FCSG325 package in the Bank Locations. Added a note and updated information regarding unused XCVR pin recommendations in the XCVR Interface. Added Figure 1-10 and Figure 1-11 in the Mechanical Drawings. Updated FCVG784 Package Pitch value to "0.8 mm" in Table 2-1, added Table 2-2 and Note in the Package Material Information.
D	09/2023	The following is a summary of the changes made in revision D of this document. Added a foot note describing that the Operating Voltage 1.1V of VDDIx (MSS DDR Bank) in Table 1-3 is for LPDDR4 support and also added a link to PolarFire Family memory Controller User Guide for more information about the LPDDR4 board design recommendations.
C	09/2022	The following is a summary of the changes made in revision C of this document. Updated Bank Locations Updated Mechanical Drawings. Updated PPAT link throughout the document. Updated Table 1-3. Added a note to mention that 12 I/Os from Bank 9 are connected to Bank 1 power supply after Table 1-1. Added Thermal Specifications Added Package Marking Updated Packing and Shipping Updated Moisture Sensitive Level (MSL)
B	05/2021	The following is a summary of the changes made in revision B of this document. Updated Table 1-1. Updated Supported I/O Features. Updated Table 1-4. Updated Table 1-5. Updated Mechanical Drawings. Updated Table 1-10. Updated Table 2-1. Updated Table 10-1.
A	03/2021	The following is a summary of the changes made in revision A of this document. The document was migrated to the Microchip template. The document number was updated to DS60001692A from 50200902. Updated Table 1-1 . Updated Table 1-2. Updated Table 1-3 . Updated Table 1-6 .
2.0	—	The following is a summary of the changes made in revision 2.0 of this document. Updated MSS I/Os. Added refer to PolarFire SoC Packaging Pin Assignment Table for the pin out information for the MSS pins. Deleted Unused Condition columns from all the details. Added refer to UG0901: PolarFire SoC FPGA Board Design Guidelines User Guide. Added LPDDR4 memory in DDR Interface. Updated Dedicated I/O Bank Pins. Added UG0901: PolarFire SoC FPGA Board Design Guidelines User Guide. Updated XCVR Interface. Added UG0901: PolarFire SoC FPGA Board Design Guidelines User Guide.
1.0	—	Initial Release.