9.9.4 Design Macro Example

  1. Make sure the design completed the Place and Route step successfully.
  2. Open SmartTime Maximum/Minimum Analysis View.
  3. Open Chip Planner.
  4. In the SmartTime Maximum Analysis View, right-click the instance Q[2] in the Timing Path Graph and choose Show in Chip Planner.
    The Properties window in Chip Planner displays the properties of Q[2].With cross-probing, the Q[2] macro is selected in Chip Planner’s Logical View and highlighted (white) in the Chip Canvas.
    Note: If Chip Planner is not open, Show in Chip Planner is gray and unavailable.
    Figure 9-4. Cross-Probing – Macro
    ???
  5. If necessary, zoom in to view the highlighted Q2 Macro in the Chip Canvas.