18.3.8 Reference Clock (REFO_CLK) Generation
The reference clock generator module uses multiple clock sources as input source and generates six different reference clock outputs.
The REFOxCON registers are used to configure the input clock source and divisor.
The clock sources for the reference clock generator:
- System clock (SYS_CLK)
- PB1 bus clock (PB1_CLK)
- 16 MHz Primary Crystal Oscillator (POSC)
- 8 MHz Fast RC Oscillator (FRC)
- 32 kHz Low Power RC Oscillator (LPRC)
- 32.768 kHz Secondary Crystal Oscillator (SOSC)
- 128 MHz system PLL (RFPLL PGM MHz, SPLL_CLK1, SPLL_CLK3)
- 96 MHz USB PLL (UPLL)
- 50 MHz Ethernet PLL (EPLL)
- REFI pin
- External clock input (REFI) is provided on anyone of the supported I/O pins. For details on supported input pins, see I/O Ports and Peripheral Pin Select (PPS) from Related Links.
The following table lists the clock's source mapping for both the CLKGEN generator and REFO_CLK generator.
| Clock Source | CLKGEN Selection (OSCCON.NOSC[3:0]) | REFO Selection (REFOxCON.ROSEL[3:0]) |
|---|---|---|
| FRC | 0000 | 0000 |
| SPLL_CLK1 | 0001 | 0001 |
| POSC (16 MHz) | 0010 | 0010 |
| SOSC | 0011 | 0011 |
| LPRC | 0100 | 0100 |
| SPLL_CLK3 (RFPLL, 128 MHz) | — | 0111 |
| PB1_CLK | — | 1001 |
| SYS_CLK | — | 1010 |
| REFI Pin | — | 1011 |
| EPLL_CLK2 | 0101 | 0101 |
| UPLL_CLK1 | 0110 | 0110 |
| EPLL_CLK1 | — | 1000 |