18.3.7 USB PLL

The USB PLL (UPLL) provides the 96 MHz double sampling clock (2*48 MHz) for the Full Speed USB module. It also manages power dissipation by turning the USB clock source on or off. The usb_clock output is enabled when the USB module is active, not suspended, and not in Sleep mode. The output should be 96 MHz when this PLL is used as the USB clock source. The FRC cannot be used as the reference clock source for the UPLL.

The UPLL output can be obtained through the UPLL feedback divider, reference frequency divider, and the first post-divider. The VCO frequency is the frequency before the UPLL post-divider, calculated as:

VCO = Ref. Clock * UPLL Feedback Divider / Reference frequency Divider

The UPLL output is then given by:

UPLL OUT = VCO / First Post Divider
Table 18-2. Configuration Parameters and Output Frequencies for UPLL
Ref. ClockReference Frequency DividerUPLL Feedback DividerVCO (MHz)Post Divider

UPLL OUT (MHz)

CLBWBandwidth Select
16196153616961 MHz010
16172115212961 MHz010
16219215361696400 KHz001
16214411521296400 KHz001
16238415361696400 KHz001
16428811521296400 KHz001

Where,

  • UPLL Feedback Divider is UPLLCON.UPLLFBDIV[9:0]
  • Reference Frequency Divider is UPLLCON.UPLLREFDIV[5:0]
  • First Post Divider is UPLLCON.UPLLPOSTDIV1[5:0]
  • Bandwidth select is UPLLBSWSEL[2:0]