18.3.6 Ethernet PLL (EPLL)

The Ethernet PLL provides 50 MHz for the Ethernet PHY, which operates at 100 Mb with two bits between the digital and PHY layers. The output should be 50 MHz when this PLL is used as the Ethernet clock source.

The clock output frequency can be obtained through EPLL feedback divider, reference frequency divider and the first post divider. VCO is the frequency before EPLL post divider and the value is calculated as:

VCO = Ref. Clock * EPLL Feedback Divider / Reference Frequency Divider

The EPLL output is then given by:

EPLL OUT = VCO / First Post Divider

There are two first post divider which corresponds to EPLL OUT1 and EPLL OUT2.

Table 18-1. Configuration Parameters and Output Frequencies for EPLL
Ref. Clock	Reference Frequency Divider	EPLL Feedback Divider	VCO (MHz)	Post Divider 1/2	EPLL OUT 1/2 (MHz)	Closed Loop Bandwidth	Bandwidth Select
16	1	100	1600	32	50	1 MHz	010
16	1	75	1200	24	50	1 MHz	010
16	2	200	1600	32	50	400 KHz	001
16	2	150	1200	24	50	400 KHz	001
16	2	100	800	16	50	400 KHz	001
16	4	400	1600	32	50	400 KHz	001
16	4	300	1200	24	50	400 KHz	001
16	4	200	800	16	50	400 KHz	001

Where,

EPLL Feedback Divider is EPLLCON.EPLLREFDIV[5:0]
Reference Frequency Divider is EPLLCON.EPLLFBDIV[9:0]
Post Divider 1 is EPLLCON.EPLLPOSTDIV1[5:0]
Post Divider 2 is APLLCON.EPLLPOSTDIV2[5:0]
Bandwidth select is EPLLBSWSEL[2:0]