18.3.1 Block Diagram

The clock system along with the PMD provides gated clock output for all peripheral buses. See Peripheral Module Disable from Related Links. The following figure illustrates the clock system block diagram.

Figure 18-1. Clock System Block Diagram
Figure 18-2. RFPLL Wrapper
Figure 18-3. Ethernet PLL Subsystem
Figure 18-4. USB PLL Subsystem
Figure 18-5. Peripheral Clock Generation (GCLK)
Figure 18-6. Low Power Clock Generation (LPCLK)

The CRU Master Clock Switch (MCS) selects which input clock is fed to the CLKGEN Synchronous Clock Generator. The CLKGEN generates and controls the synchronous clocks on the system. This includes the CPU, bus clocks (APB and AHB) and the synchronous (to the CPU) user interfaces of the peripherals. It contains prescalers for the CPU and bus clocks.