18.3.9 Peripheral Clock Generation (GCLK)

All six reference clock generator outputs are given as input for GCLK generator module for peripheral clock generation. The GCLK module provides selection among following clocks:

REFO1 to REFO6 clocks

Note: Only REFO1 – REFO4 can get routed to chip IOs.
Low-power clock (32KHz_LPCLK) (either LPRC, SOSC or 32 KHz clock derived from POSC/FRC)

The GCLK generator provides the Generic Clocks (GCLK_<Periperhal>) for system peripherals via peripheral channels. There are a total of 26 peripheral channels with the mapping as shown in the following table. The peripheral channels are fixed configuration and mapped in the CFGPCLKGENx register. CFGPCLKGENx dictates the peripheral clock selection and enables the clock for a specific peripheral. For details about the position in CFGPCLKGENx, see Register Summary of the System Configuration and Register Locking (CFG) from Related Links.

Table 18-4. Peripheral Clock Generation
Peripheral Clock	Channel Index
GCLK_EIC, GCLK_CCL	0
GCLK_FREQM_MSR	1
GCLK_FREQM_REF	2
GCLK_SERCOM2_CORE	3
GCLK_SERCOM0_CORE, GCLK_SERCOM1_CORE	4
GCLK_SERCOM2_CORE	4
GCLK_SERCOM2_CORE	5
GCLK_TC0	6
GCLK_TC1	7
GCLK_TC2, GCLK_TC3	8
GCLK_TC4, GCLK_TC5	9
GCLK_TC6, GCLK_TC7	10
GCLK_TC8, GCLK_TC9	11
GCLK_EVSYS_CH_0	12
GCLK_EVSYS_CH_1	13
GCLK_EVSYS_CH_2	14
GCLK_EVSYS_CH_3	15
GCLK_EVSYS_CH_4	16
GCLK_EVSYS_CH_5	17
GCLK_EVSYS_CH_6	18
GCLK_EVSYS_CH_7	19
GCLK_EVSYS_CH_8	20
GCLK_EVSYS_CH_9	21
GCLK_EVSYS_CH_10	22
GCLK_EVSYS_CH_11	23
GCLK_TCC0	24
GCLK_TCC1, GCLK_TCC2	25
GCLK_AC	26
GCLK_CM4_TRACE	27
GCLK_CAN0	28
GCLK_CAN1	29
GCLK_ETH_TSU	30
GCLK_CVD	31

The following figure illustrates an example, where SPLL_CLK1 clocks the SERCOM0. The SPLL_CLK1 is input to the REFO generator. The Generic Clock Generator uses the REFO_CLK1 as its clock source and feeds into Peripheral Channel 3. The Generic Clock channel 3, also called GCLK_SERCOM0_CORE, is connected to SERCOM0. The SERCOM0 interface is clocked by PB1_CLK bus clock.