37.5.5 Selecting the Scanned Inputs

All available analog inputs can be configured for scanning. Class 1 inputs are sampled using their dedicated ADC core. Class 2 and Class 3 inputs are sampled using the shared ADC core. A single conversion trigger source is selected for all of the inputs selected for scanning using the STRGSRC[4:0] bits (ADCCON1[20:16]). On each conversion trigger, the ADC core starts converting (in the natural priority) all inputs specified in the user-specified scan list (ADCCSS1). For Class 2 and Class 3 inputs, the trigger initiates a sequential sample/conversion process in the natural priority order.

An analog input belongs to the scan if it is:
  • A Class 3 input. For Class 3 inputs, scan is the only mechanism for conversion.
  • A Class 1 and Class 2 input that has the scan trigger selected as the trigger source by selecting the STRIG option in the TRGSRCx[4:0] bits located in the ADCTRG1 and ADCTRG2 registers

The trigger options available for scan are identical to those available for independent triggering of Class 1 and Class 2 inputs. Any Class 2 inputs that are part of the scan must have the STRIG option selected as their trigger source in the TRGSRCx[4:0] bits.

Note: The End-of-Scan (EOS) is generated only after completing the conversion of all inputs selected in CSSx register. Until meeting this condition, the scan sequence is still in effect. Therefore, the user can use the EOS interrupt for any scan sequence with any combination of input types.
The following code is an example for ADC scanning multiple inputs.
// Default 12bits resolution
ADCHS_REGS->ADCHS_ADCCON1 = 0x600000;
// Shared SAR ADC Core Clock and sampling
ADCHS_REGS->ADCHS_ADCCON2 = 0x20001;
// ADC clock clock divider
ADCHS_REGS->ADCHS_ADCCON3 = 0x1000000;

// No Trigger 1
ADCHS_REGS->ADCHS_ADCTRG1 = 0x0; 

// Set AN4 and AN6 (Class 2) to trigger from scan source
ADCHS_REGS->ADCHS_ADCTRG2 = 0x30003; 
    
// Positive edge
ADCHS_REGS->ADCHS_ADCTRGSNS = 0x0;
// Single ended , unsigned data
ADCHS_REGS->ADCHS_ADCIMCON1 = 0x0;
ADCHS_REGS->ADCHS_ADCIMCON2 = 0x0;  
    

/* Turn ON ADC */
ADCHS_REGS->ADCHS_ADCCON1 |= ADCHS_ADCCON1_ON_Msk;
while((ADCHS_REGS->ADCHS_ADCCON2 & ADCHS_ADCCON2_BGVRRDY_Msk) == ADCHS_ADCCON2_BGVRRDY_Msk)
{
    // Wait until the reference voltage is ready
}
// Wait if there is a fault with the reference voltage
while((ADCHS_REGS->ADCHS_ADCCON2 & ADCHS_ADCCON2_REFFLT_Msk) == ADCHS_ADCCON2_REFFLT_Msk)
{
}

// ADC 7 setup
// Enable the clock to analog bias
ADCHS_REGS->ADCHS_ADCANCON |= ADCHS_ADCANCON_ANEN7_Msk;      

 // Wait until ADC is ready
while(((ADCHS_REGS->ADCHS_ADCANCON & ADCHS_ADCANCON_WKRDY7_Msk)) == 0U)
{
        /* Nothing to do */
}

// Enable ADC
ADCHS_REGS->ADCHS_ADCCON3 |= ADCHS_ADCCON3_DIGEN7_Msk;

// GlobalEdgeConversionStart
ADCHS_REGS->ADCHS_ADCCON3 |= ADCHS_ADCCON3_GSWTRG_Msk;

// Wait Channel 4 and 6 conversion
while(!
((ADCHS_REGS->ADCHS_ADCDSTAT1 >> 4) & 0x01U) != 0U)
while(!
((ADCHS_REGS->ADCHS_ADCDSTAT1 >> 6) & 0x01U) != 0U)

// Get Channel 4 and 6 result:
result = ADCHS_ADCDATA4;
result = ADCHS_ADCDATA6;