37.5.3 Selecting the Format of the ADC Result

The data in the ADC Result register can be read in any of the four supported data formats. The user can select from unsigned integer, signed integer, unsigned fractional or signed fractional. Integer data is right-justified and fractional data is left-justified.

• The integer or fractional data format selection is specified globally for all analog inputs using the Fractional Data Output Format bit, FRACT (ADCCON1[23]).
• The signed or unsigned data format selection can be independently specified for each individual analog input using the SIGNx bits in the ADCIMCONx registers.

The following code is an example for ADC Class 2 configuration and fractional format.

// Default 12bits resolution
ADCHS_REGS->ADCHS_ADCCON1 = 0x600000;
// Shared SAR ADC Core Clock and sampling
ADCHS_REGS->ADCHS_ADCCON2 = 0x20001;
// ADC clock clock divider
ADCHS_REGS->ADCHS_ADCCON3 = 0x1000000;

// No Trigger 1
ADCHS_REGS->ADCHS_ADCTRG1 = 0x0; 

// Trigger 2 to Global level software trigger
ADCHS_REGS->ADCHS_ADCTRG2 = 0x1; 
    
// Positive edge
ADCHS_REGS->ADCHS_ADCTRGSNS = 0x0;
// Single ended , unsigned data
ADCHS_REGS->ADCHS_ADCIMCON1 = 0x0;
ADCHS_REGS->ADCHS_ADCIMCON2 = 0x0;  
    

// No Input scan 
ADCHS_REGS->ADCHS_ADCCSS1 = 0x0;
    
// Turn ON ADC
ADCHS_REGS->ADCHS_ADCCON1 |= ADCHS_ADCCON1_ON_Msk;

// Wait until the reference voltage is ready
while((ADCHS_REGS->ADCHS_ADCCON2 & ADCHS_ADCCON2_BGVRRDY_Msk) == ADCHS_ADCCON2_BGVRRDY_Msk)
{
}

// Wait if there is a fault with the reference voltage
while((ADCHS_REGS->ADCHS_ADCCON2 & ADCHS_ADCCON2_REFFLT_Msk) == ADCHS_ADCCON2_REFFLT_Msk)
{
}

// ADC 7 setup
// Enable the clock to analog bias
ADCHS_REGS->ADCHS_ADCANCON |= ADCHS_ADCANCON_ANEN7_Msk;      

 // Wait until ADC is ready
while(((ADCHS_REGS->ADCHS_ADCANCON & ADCHS_ADCANCON_WKRDY7_Msk)) == 0U)
{
        /* Nothing to do */
}

// Enable ADC
ADCHS_REGS->ADCHS_ADCCON3 |= ADCHS_ADCCON3_DIGEN7_Msk;

// GlobalEdgeConversionStart
ADCHS_REGS->ADCHS_ADCCON3 |= ADCHS_ADCCON3_GSWTRG_Msk;

// Wait Channel 4 conversion
while(!
((ADCHS_REGS->ADCHS_ADCDSTAT1 >> 4) & 0x01U) != 0U)

// Get Channel 4 result:
result = ADCHS_ADCDATA4;