46.6.1.1 QEI Control Register

Note:

When CCMx = 01, CCMx = 10 or CCMx = 11, all of the QEI Counters operate as timers and the PIMOD[2:0] bits are ignored.
When CCMx = 00, and QEA and QEB values match the Index Match Value (IMV), the POSxCNTH and POSxCNTL registers are reset.
The selected clock rate should be at least twice the expected maximum quadrature count rate.
The QCAPEN and HCAPEN bits must be cleared during PIMOD modes 2 though 7 to insure proper functionality.

Name:	QEICON
Offset:	0x00000000
Reset:	0x00000000


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
	QEIEN		QEISIDL	PIMOD[2:0]			IMV[1:0]
Access	R/W		R/W	R/W	R/W	R/W	R/W	R/W
Reset	0		0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
		INTDIV[2:0]			CNTPOL	GATEN	CCM[1:0]
Access		R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset		0	0	0	0	0	0	0

Bit 15 – QEIEN Quadrature Encoder Interface Module Counter Enable bit

Value	Description
1	Module counters are enabled
0	Module counters are disabled, but SFRs can be read or written

Bit 13 – QEISIDL QEI Stop in Idle Mode bit

Value	Description
1	Discontinues module operation when device enters Idle mode
0	Continues module operation in Idle mode

Bits 12:10 – PIMOD[2:0] Position Counter Initialization Mode Select bits⁽¹⁾

Value	Description
111	Modulo Count mode for position counter and every Index input event resets the position counter
110	Modulo Count mode for position counter
101	Position counter equals ICC register resets the position counter
100	Second Index event after Home event initializes position counter with contents of QEIxIC register
011	First Index event after Home event initializes position counter with contents of QEIxIC register
010	Next index input event initializes the position counter with contents of QEIxIC register
001	Every index input event resets the position counter
000	Index input event does not affect position counter

Bits 9:8 – IMV[1:0] Index Match Value bits⁽²⁾

Value	Description
11	Index match occurs when QEB = `1` and QEA = `1`
10	Index match occurs when QEB = `1` and QEA = `0`
01	Index match occurs when QEB = `0` and QEA = `1`
00	Index match occurs when QEB = `0` and QEA = `0`

Bits 6:4 – INTDIV[2:0] Timer Input Clock Prescale Select bits⁽³⁾

(Interval Timer, Main Timer (Position Counter), Velocity Counter and Index Counter internal clock divider select)

Value	Description
111	1:128 prescale value
110	1:64 prescale value
101	1:32 prescale value
100	1:16 prescale value
011	1:8 prescale value
010	1:4 prescale value
001	1:2 prescale value
000	1:1 prescale value

Bit 3 – CNTPOL Position and Index Counter/Timer Direction Select bit

Value	Description
1	Counter direction is negative unless modified by external up/down signal
0	Counter direction is positive unless modified by external up/down signal

Bit 2 – GATEN External Count Gate Enable bit

Value	Description
1	External gate signal controls Position Counter operation
0	External gate signal does not affect Position Counter/timer operation

Bits 1:0 – CCM[1:0] Counter Control Mode Selection bits

Value	Description
11	Internal Timer mode
10	External Clock Count with External Gate mode
01	External Clock Count with External Up/Down mode
00	Quadrature Encoder mode

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