46.6.1 Register Summary

Note: All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See CLR, SET, and INV Registers from Related Links.


Offset	Name	Bit Pos.	7	6	5	4	3	2	1	0
0x00	QEICON	7:0		INTDIV[2:0]			CNTPOL	GATEN	CCM[1:0]
		15:8	QEIEN		QEISIDL	PIMOD[2:0]			IMV[1:0]
		23:16
		31:24
0x04 ... 0x0F	Reserved
0x10	QEIIOC	7:0	HOMPOL	IDXPOL	QEBPOL	QEAPOL	HOME	INDEX	QEB	QEA
		15:8	QCAPEN	FLTREN	QFDIV[2:0]			OUTFNC[1:0]		SWPAB
		23:16								HCAPEN
		31:24
0x14 ... 0x1F	Reserved
0x20	QEISTAT	7:0	PCIIRQ	PCIIEN	VELOVIRQ	VELOVIEN	HOMIRQ	HOMIEN	IDXIRQ	IDXIEN
		15:8			PCHEQIRQ	PCHEQIEN	PCLEQIRQ	PCLEQIEN	POSOVIRQ	POSOVIEN
		23:16
		31:24
0x24 ... 0x2F	Reserved
0x30	POSCNT	7:0	POSCNT[7:0]
		15:8	POSCNT[15:8]
		23:16	POSCNT[23:16]
		31:24	POSCNT[31:24]
0x34 ... 0x3F	Reserved
0x40	POSHLD	7:0	POSHLD[7:0]
		15:8	POSHLD[15:8]
		23:16	POSHLD[23:16]
		31:24	POSHLD[31:24]
0x44 ... 0x4F	Reserved
0x50	VELCNT	7:0	VELCNT[7:0]
		15:8	VELCNT[15:8]
		23:16	VELCNT[23:16]
		31:24	VELCNT[31:24]
0x54 ... 0x5F	Reserved
0x60	VELHLD	7:0	VEL_HLD[7:0]
		15:8	VEL_HLD[15:8]
		23:16	VEL_HLD[23:16]
		31:24	VEL_HLD[31:24]
0x64 ... 0x6F	Reserved
0x70	INTTMR	7:0	INTTMR[7:0]
		15:8	INTTMR[15:8]
		23:16	INTTMR[23:16]
		31:24	INTTMR[31:24]
0x74 ... 0x7F	Reserved
0x80	INTHLD	7:0	INTHLD[7:0]
		15:8	INTHLD[15:8]
		23:16	INTHLD[23:16]
		31:24	INTHLD[31:24]
0x84 ... 0x8F	Reserved
0x90	INDXCNT	7:0	INDXCNT[7:0]
		15:8	INDXCNT[15:8]
		23:16	INDXCNT[23:16]
		31:24	INDXCNT[31:24]
0x94 ... 0x9F	Reserved
0xA0	INDXHLD	7:0	INDXHLD[7:0]
		15:8	INDXHLD[15:8]
		23:16	INDXHLD[23:16]
		31:24	INDXHLD[31:24]
0xA4 ... 0xAF	Reserved
0xB0	QEIICC	7:0	ICCH[7:0]
		15:8	ICCH[15:8]
		23:16	ICCH[23:16]
		31:24	ICCH[31:24]
0xB4 ... 0xBF	Reserved
0xC0	QEICMPL	7:0	CMPL[7:0]
		15:8	CMPL[15:8]
		23:16	CMPL[23:16]
		31:24	CMPL[31:24]