46.6.1.4 Position Counter Word Register

Name:	POSCNT
Offset:	0x30
Reset:	0x00000000
Property:	RW


Bit	31	30	29	28	27	26	25	24
	POSCNT[31:24]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	POSCNT[23:16]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	POSCNT[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	POSCNT[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 31:0 – POSCNT[31:0] 32-Bit Position Counter Register (POSxCNT) bits

The Operating mode of the position counter is controlled by the CCM bit in the QEIxCON register.

Quadrature Count mode: The QEA and QEB inputs are decoded to generate count pulses and direction information for controlling the position counter operation.

External Count with External Up/Down mode: The QEA/EXTCNT input is treated as an external count signal, and the QEB/DIR/GATE input provides the count direction information.

External Count with External Gate mode: The QEA/EXTCNT input is treated as an external count signal. If the GATEN bit in the QEIxCON register is equal to ‘1’, the QEB/DIR/GATE input will gate the counter signal.

Internal Timer mode: The position counter uses PBCLK2 divided by the clock divider INTDIV as the count source.