46.6.1.3 QEI Status Register
Note:
- This status bit is only applicable to PIMOD[2:0] modes,
‘
011’ and ‘100’.
| Name: | QEISTAT |
| Offset: | 0x20 |
| Reset: | 0x00000000 |
| Property: | R/W |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PCHEQIRQ | PCHEQIEN | PCLEQIRQ | PCLEQIEN | POSOVIRQ | POSOVIEN | ||||
| Access | RC | R/W | RC | R/W | RC | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PCIIRQ | PCIIEN | VELOVIRQ | VELOVIEN | HOMIRQ | HOMIEN | IDXIRQ | IDXIEN | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 13 – PCHEQIRQ Position Counter Becomes Greater Than Compare Status bit
| Value | Description |
|---|---|
| 1 | POSxCNT > QEIxICCH |
| 0 | POSxCNT ≤ QEIxICCH |
Bit 12 – PCHEQIEN Position Counter Becomes Greater Than Compare Interrupt Enable bit
| Value | Description |
|---|---|
| 1 | Interrupt is enabled |
| 0 | Interrupt is disabled |
Bit 11 – PCLEQIRQ Position Counter Becomes Less Than Compare Status bit
| Value | Description |
|---|---|
| 1 | POSxCNT < QEIxCMPL |
| 0 | POSxCNT ≥ QEIxCMPL |
Bit 10 – PCLEQIEN Position Counter Becomes Less Than Compare Interrupt Enable bit
| Value | Description |
|---|---|
| 1 | Interrupt is enabled |
| 0 | Interrupt is disabled |
Bit 9 – POSOVIRQ Position Counter Overflow Status bit
| Value | Description |
|---|---|
| 1 | Overflow has occurred |
| 0 | No overflow has occurred |
Bit 8 – POSOVIEN Position Counter Overflow Interrupt Enable bit
| Value | Description |
|---|---|
| 1 | Interrupt is enabled |
| 0 | Interrupt is disabled |
Bit 7 – PCIIRQ Position Counter (Homing) Initialization Process Complete Status bit(1)
| Value | Description |
|---|---|
| 1 | POSxCNT was reinitialized |
| 0 | POSxCNT was not reinitialized |
Bit 6 – PCIIEN Position Counter (Homing) Initialization Process Complete Interrupt Enable bit
| Value | Description |
|---|---|
| 1 | Interrupt is enabled |
| 0 | Interrupt is disabled |
Bit 5 – VELOVIRQ Velocity Counter Overflow Status bit
| Value | Description |
|---|---|
| 1 | Overflow has occurred |
| 0 | No overflow has occurred |
Bit 4 – VELOVIEN Velocity Counter Overflow Interrupt Enable bit
| Value | Description |
|---|---|
| 1 | Interrupt is enabled |
| 0 | Interrupt is disabled |
Bit 3 – HOMIRQ Status Flag for Home Event Status bit
| Value | Description |
|---|---|
| 1 | Home event has occurred |
| 0 | No Home event has occurred |
Bit 2 – HOMIEN Home Input Event Interrupt Enable bit
| Value | Description |
|---|---|
| 1 | Interrupt is enabled |
| 0 | Interrupt is disabled |
Bit 1 – IDXIRQ Status Flag for Index Event Status bit
| Value | Description |
|---|---|
| 1 | Index event has occurred |
| 0 | No Index event has occurred |
Bit 0 – IDXIEN Index Input Event Interrupt Enable bit
| Value | Description |
|---|---|
| 1 | Interrupt is enabled |
| 0 | Interrupt is disabled |