In this mode, the velocity, index and interval counter of the position counter uses an
internal clock as the count source. The internal clock is divided by the clock divider using
the INTDIV<2:0> bits (QEIxCON<6:4>). If the GATEN bit (QEIxCON<2>) is set,
and QEB/DIR/GATE = 0, the QEB/DIR/GATE input will inhibit the counter
signal. If the GATEN bit is cleared, the gate signal does not affect the operation of the
counter. The default count direction is positive. If the CNTPOL bit (QEIxCON<3>) is
set, the count direction is negative. The following figure illustrates the timing diagram of
an Internal Timer mode operation. Figure 46-5. Internal Timer Mode
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