6 Pinout and Signal Descriptions List

This following table provides detailed signal names classified by the peripherals along with the device pinout for the PIC32CX-BZ6 and the PIC32WM-BZ6 Module.

Table 6-1. PIC32CX2051BZ62132 Pinout and Signal Descriptions List
SoC (PIC32CX2051BZ62132)Module (PIC32WM-BZ6204)Pin Name
A73(3)A7, A10, A13, A24, A33, A42, A43, A49, B26GND
A1A34, A35, A36, A37, A38, A39, A40, A41, B30, B31, B32, B33No connection
B1—No connection
A2—No connection
B2A16QSPI_DATA0/RTC_IN3/RPA0/IOCA0/RA0
A3A25, B22(12)pmu_vddio/vpmu_vddc (PMU core circuit power; 1.9-3.6V)
B3—No connection
A4B14QSPI_SCK/RTC_IN2/RPA1/IOCA1/RA1
A5A17QSPI_DATA3/RTC_IN1/RPA2/IOCA2/RA2
B4A12SERCOM0_PAD0/RPA5/IOCA5/RA5
A6B13RPD0/IOCD0/RD0
B5A15RPD1/IOCD1/RD1
A7A25, B22(12)FAVDD/VDDIO(VDD33)
B6—No connection
A8B10SERCOM0_PAD1/RPA6/IOCA6/RA6
B7—No connection
A9A19VBUSON/SERCOM1_PAD0/TRCLK/RPA7/IOCA7/RA7
B8—No connection
A10B17CAN0_TX/SERCOM1_PAD1/RPA8/IOCA8/RA8
B9—No connection
A11A20CAN0_RX/RTC_IN0_ALT/SERCOM1_PAD2/RPA9/IOCA9/RA9
B10—No connection
A12A25, B22(12)VDDIO (VDD33)
B11—No connection
A13B19RTC_OUT_ALT/SERCOM1_PAD3/RPA10/IOCA10/RA10
B12B15QSPI_DATA1/RPB12/IOCB12/RB12
A14A27GMAC_GCRS_DV/RPE2/IOCE2/RE2
A15A26GMAC_GTXEN/RPC9/IOCC9/RC9
B13B23GMAC_GRXER/RPC8/IOCC8/RC8
A16A23RPC10/IOCC10/RC10
B14A22RPE3/IOCE3/RE3
A17—No connection
B15—No connection
A18—No connection
A19—No connection
B16—No connection
A20—No connection
B17B28INT0/SERCOM0_PAD2/CM4_SWDIO/RPB9/IOCB9/RB9
A21B16RTC_EVENT/QSPI_CS/RPB13/IOCB13/RB13
B18A21USBID/RTC_OUT/SERCOM0_PAD3/RPA4/IOCA4/RA4
A22A32CM4_SWCLK/RPB8/IOCB8/RB8
B19B25GMAC_GRX0/I2C_SERCOM_PAD1/ANN0/RPA14/IOCA14/RA14
A23A29GMAC_GRX1/I2C_SERCOM_PAD0/RPA13/IOCA13/RA13
A24A25, B22(12)VDDIO (VDD33)
B20A25, B22(12)VDDIO (VDD33)
A25A30GMAC_GREFCLKOUT/SERCOM2_PAD3/RPC1/IOCC1/RC1
B21A31GMAC_GTX0/SERCOM2_PAD2/RPC0/IOCC0/RC0
A26B27GMAC_GTX1/SERCOM2_PAD1/RPE1/IOCE1/RE1
B22B20SERCOM2_PAD0/RPE0/IOCE0/RE0
A27A18ANA0/QSPI_DATA2/RPB11/IOCB11/RB11
B23—No connection
A28B21USBOEN/AN0/RPB10/IOCB10/RB10
B24—No connection
A29—No connection
B25—No connection
A30—No connection
B26—No connection
A31—CLDO_IN (secondary digital power supply; 1.2V)
B27—No connection
A32—XO_N
B28—No connection
A33—XO_P
B29—No connection
A34—VDD_RF (RF block power supply)
B30—No connection
A35—No connection
A36—No connection
A37—No connection
A38—No connection
B31—No connection
A39—CLDO_OUT (core LDO power supply; 1.2V)
B32—No connection
A40—RFLDO_OUT (RF LDO power supply; 1.2V)
B33—No connection
A41—CLDO_BUCK (RF/DIG CLDO supply)
B34—No connection
A42—BUCK_PA (RF PA supply);

Filtered version of PMU output

B35—No connection
A43—RF_IO
B36—No connection
A44—No connection
B37A45CVDT0/CVDRP16/CVD16/AN16/RPD2/IOCD2/RD2
A45A44CVDT14/CVDRP14/CVD14/AN14/RPE6/IOCE6/RE6
B38B18ANB0/RPE5/IOCE5/RE5
A46A14RPE4/IOCE4/RE4
B39B6RPC11/IOCC11/RC11
A47A25, B22(12)VDDIO (VDD33)
B40B4CVDT2/CVDR2/CVD2/AN2(5)/RPB6/IOCB6/RB6
A48B12RTC_IN0/ANN1/DACOUT/RPA3/IOCA3/RA3
B41B2AC_AIN0/CVDT6/CVDRP6/CVD6/AN6/RPB2/IOCB2/RB2
A49B3CVDT8/CVDRP8/CVD8/AN8(5)/RPB4/IOCB4/RB4
B42A48CVDT9/CVDRP9/CVD9/AN9/RPD3/IOCD3/RD3
A50A46CVDT11/CVDRP11/CVD11/AN11/RPD5/IOCD5/RD5
B43A3AC_AIN1/CVDT7/CVDR7/CVD7/AN7/RPB3/IOCB3/RB3
A51A47VBUS
B44—No connection
A52A1AVDD(8)
B45B29RPA15/IOCA15/RA15
A53—No connection
A54—No connection
A55—No connection
A56—No connection
B46A5LVDIN/CVDT3/CVDRP3/CVD3/AN3/CM4_SWO/RPB7/IOCB7/RB7
A57A11CVDT10/CVDRP10/CVD10/AN10/RPD4/IOCD4/RD4
B47—No connection
A58A25, B22(12)VDDIO (VDD33)/VUSB3V3
B48B8CVDT16/CVDRP17/CVD17/AN17/RPB15/IOCB15/RB15
A59A9CVDT17/CVDRP18/CVD18/AN18/RPB14/IOCB14/RB14
B49B1AC_AIN2/CVDT4/CVDRP4/CVD4/AN4/RPB0/IOCB0/RB0
B50—No connection
A60B5D+
B51A2AC_AIN3/CVDT5/CVDRP5/CVD5/AN5/RPB1/IOCB1/RB1
A61A6D-
B52—No connection
A62—PLL_VDD
A63—SOC_LDO_VDD
B53—No connection
A64—SOC_LDO_VDD
B54—No connection
A65A28GMAC_GMDIO/CVDT12/CVDRP12/CVD12/AN12/RPD6/IOCD6/RD6
B55B24GMAC_GMDC/CVDT13/CVDRP13/CVD13/AN13/RPD7/IOCD7/RD7
A66B9CVDT15/CVDRP15/CVD15/AN15/RPC7/IOCC7/RC7
B56A4CVDT1/CVDRP1/CVD1/AN1(5)/RPB5/IOCB5/RB5
A67B11MCLR
B57B7SOSCI/RPA11/RA11(4)
A68A8SOSCO/RPA12/RA12(4)
A69—PMU_MLDO_OUT
B58—No connection
A70A25, B22(12)VPMU_VDDP
B59—No connection
A71—No connection
B60—PMU_BK_LX
A72—No connection
Note:
  1. The remappable peripherals can use all GPIOs (RPAn, RPBn, RPCn, RPDn and RPEn) via PPS.
  2. All GPIOs (RPAn, RPBn, RPCn, RPDn, and RPEn) can be used for I/O Change Notification (IOCAn, IOCBn, IOCCn, IOCDn and IOCEn).
  3. Connect the metal paddle at the bottom of the device to the system ground.
  4. If not using SOSC, use this pin as an input-only pin.
  5. JTAG is the default functionality on these pins. It is recommended to write 0 to the CFGCON0.JTAGEN register during application initialization to use these pins for regular GPIO functionality.
  6. A pull-up resistor (10K) on the SWCLK pin is critical for reliable operation.
  7. For more details on power supply pin connections and the filtering components, refer to the Design Package available on the product page.
  8. Provide filtered version of main supply input.
  9. These I/O pins are 5.5V tolerant:
    • MCLR, PA0, PA1, PA2, PA4, PA5, PA6, PA7, PA8, PA10, PA13, PA15, PB3, PB12, PB13, PC0, PC1, PC8, PC9, PC10, PC11, PD0, PD1, PE0, PE1, PE2, PE3 and PE4.
    • All other I/O pins are 3.3V tolerant.
  10. The following is the grouping of the pins based on their drive strength:
    • 4x drive strength: PE2, PC8, PE3, PC10, PB8, PB10, PD2, PE6, PE5, PE4, PC11, PB6, PA3, PB2, PB4, PD3, PD5, PB3, PA15, PB7, PD4, PB15, PB14,PB0,PB1, PD6, PD7, PC7 and PB5.
    • 8x drive strength: PA0, PA1, PA2, PA4, PA5, PA6, PA7, PA8, PA9. PA10, PA13, PA14, PB12, PB13, PB9, PE0 and PB11.
    • 12x drive strength: PD0, PD1, PC9, PC1, PC0 and PE1.
  11. Enabling high-frequency digital I/O can affect radio frequency parameters, such as receiver sensitivity. Operate the following GPIOs at the frequencies mentioned below to help maintain optimal radio performance.
    • RB0, RB1, RB2, RB3, RD3, RE2 and RD6 ≤ 1 MHz
    • RD0, RD2, RD1, RD7, RC8, RC1 and RE3 ≤ 500 KHz
  12. The module power supply pin name is VDD.
Table 6-2. PIC32CX2051BZ66048 Pinout and Signal Descriptions List
SoC (PIC32CX2051BZ66048) Pin NumberModule (PIC32WM-BZ6602) Pin NumberPin Function
1P21 and P22(12)PMU_VDDIO/VPMU_VDDC (PMU core circuit power; 1.9-3.6V)
2P13QSPI_DATA0/RTC_IN3/RPA0/IOCA0/RA0
3P14QSPI_SCK/RTC_IN2/RPA1/IOCA1/RA1
4P16QSPI_DATA3/RTC_IN1/RPA2/IOCA2/RA2
5P19SERCOM0_PAD0/RPA5/IOCA5/RA5
6P21 and P22(12)FAVDD/VDDIO (VDD33)
7P20PGC2/SERCOM0_PAD1/RPA6/IOCA6/RA6
8P24TRCLK/SERCOM1_PAD0/RPA7/IOCA7/RA7
9P25CAN0_TX/PGD2/SERCOM1_PAD1/RPA8/IOCA8/RA8
10P26CAN0_RX/SERCOM1_PAD2/RTC_IN0_ALT/RPA9/IOCA9/RA9
11P27SERCOM1_PAD3/RTC_OUT_ALT/RPA10/IOCA10/RA10
12P18QSPI_DATA1/RPB12/IOCB12/RB12
13P17QSPI_CS/RTC_EVENT/RPB13/IOCB13/RB13
14P38CM4_SWDIO/SERCOM0_PAD2/INT0/RPB9/IOCB9/RB9
15P37CM4_SWCLK/RPB8/IOCB8/RB8
16P30SERCOM0_PAD3/RTC_OUT/RPA4/IOCA4/RA4
17P28I2C_SERCOM_PAD0/RPA13/IOCA13/RA13
18P29ANN0/I2C_SERCOM_PAD1/RPA14/IOCA14/RA14
19P12ANA0/QSPI_DATA2/RPB11/IOCB11/RB11
20P11AN0/RPB10/IOCB10/RB10
21—CLDO_IN (secondary digital power supply; 1.2V)
22—XO_N
23—XO_P
24—VDD_RF (RF block power supply)
25—CLDO_OUT (core LDO power supply; 1.2V)
26—RFLDO_OUT (RF LDO power supply; 1.2V)
27—CLDO_BUCK (RF/DIG CLDO supply)
28—BUCK_PA (RF PA supply)
29—RF_IO
30—No Connection
31P39PGD1/AN2(5)/CVD2/CVDR2/CVDT2/RPB6/IOCB6/RB6
32P42ANN1/RTC_IN0/DACOUT/RPA3/IOCA3/RA3
33P43AC_AIN0/AN6/CVD6/CVDR6/CVDT6/RPB2/IOCB2/RB2
34P44PGC4/AN8(5)/CVD8/CVDR8/CVDT8/RPB4/IOCB4/RB4
35P45AC_AIN1/AN7/CVD7/CVDR7/CVDT7/RPB3/IOCB3/RB3
36P4AVDD(8)
37P10LVDIN/PGC1/AN3/CVD3/CVDR3/CVDT3/RPB7/IOCB7/RB7
38P21 and P22(12)VDDIO (VDD33)
39P46AC_AIN2/AN4/CVD4/CVDR4/CVDT4/RPB0/IOCB0/RB0
40P1AC_AIN3/AN5/CVD5/CVDR5/CVDT5/RPB1/IOCB1/RB1
41—SOC_LDO_VDD
42P2PGD4/ AN1(5)/CVD1 /CVDR1/CVDT1/RPB5/IOCB5/RB5
43P3MCLR
44P7SOSCI/RPA11/RA11(4)
45P8SOSCO/RPA12/RA12(4)
46—PMU_MLDO_OUT
47P21 and P22(12)VPMU_VDD
48—PMU_BK_LK
0(3)0(3), P5, P6, P9, P15, P23, P31, P32, P33, P34, P35, P36, P40, P41, P47, P48, P49 and P50Ground
Note:
  1. The remappable peripherals can use GPIOs (RPAn and RPBn) via PPS.
  2. Use GPIOs (RPAn and RPBn) for I/O change notification (IOCAn and IOCBn).
  3. Connect the metal paddle at the bottom of the device to the system ground.
  4. If not using SOSC, use this pin as an input-only pin.
  5. JTAG is the default functionality on these pins. It is recommended to write ‘0’ to the CFGCON0.JTAGEN register during application initialization to use these pins for regular GPIO functionality.
  6. A pull-up resistor (10K) on the SWCLK pin is critical for reliable operation.
  7. For more details on power supply pin connections and the filtering components, refer to the Design Package available on the product page.
  8. Provide a filtered version of the main supply input.
  9. These I/O pins are 5.5V tolerant:
    • MCLR, PA0, PA1, PA2, PA4, PA5, PA6, PA7, PA8, PA10, PA13, PB3, PB12 and PB13.
    • All other I/O pins are 3.3V tolerant.
  10. The following is the grouping of the pins based on their drive strength:
    • 4X drive strength: PA3, PB1, PB2, PB3, PB8, PB6, PB4, PB0, PB10, PB7 and PB5
    • 8X drive strength: PA10, PA13, PA14, PA4, PB9, PA9, PA8, PA7, PA6, PA5, PB12, PB13, PA2, PA1, PA0 and PB11.
  11. Enabling high-frequency digital I/O can affect radio frequency parameters, such as receiver sensitivity. Operate the following GPIOs at the frequencies mentioned below to help maintain optimal radio performance.
    • PB10 ≤ 500 KHz
    • PB1 and PB0 ≤ 2 MHz
    • PB2 and PB3 ≤ 1 MHz
  12. The module power supply pin name is VDD.