2.1.3 I/O Power-Up and Supply Voltage Thresholds for Power-On Reset (Military)

Sophisticated power-up management circuitry is designed into every SmartFusion cSoC. These circuits ensure easy transition from the powered-off state to the powered-up state of the device. In addition, the I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-2.

There are five regions to consider during power-up.

SmartFusion I/Os are activated only if ALL of the following three conditions are met:
  1. VCC and VCCxxxxIOBx are above the minimum specified trip points (Figure 2-2).
  2. VCCxxxxIOBx > VCC – 0.75V (typical)
  3. Chip is in the SoC Mode.
VCCxxxxIOBx Trip Point:
  • Ramping up: 0.6V < trip_point_up < 1.2V

  • Ramping down: 0.5V < trip_point_down < 1.1V
VCC Trip Point:
  • 
Ramping up: 0.6V < trip_point_up < 1.1V

  • Ramping down: 0.5V < trip_point_down < 1V

VCC and VCCxxxxIOBx ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following:

  • During programming, I/Os become tristated and weakly pulled up to VCCxxxxIOBx.
  • JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O behavior.