2.3.3 Detailed I/O DC Characteristics

(Ask a Question)

Table 2-26. Input Capacitance
Symbol	Definition	Conditions	Min.	Max.	Units
C_IN	Input capacitance	V_IN = 0, f = 1.0 MHz	—	8	pF
C_INCLK	Input capacitance on the clock pin	V_IN = 0, f = 1.0 MHz	—	8	pF

Table 2-27. I/O Output Buffer Maximum Resistances¹ Applicable to FPGA I/O Banks
Standard	Drive Strength	RPULL-DOWN (Ω)²	RPULL-UP (Ω)³
3.3V LVTTL / 3.3V LVCMOS	2 mA	100	300
	4 mA	100	300
	6 mA	50	150
	8 mA	50	150
	12 mA	25	75
	16 mA	17	50
	24 mA	11	33
2.5V LVCMOS	2 mA	100	200
	4 mA	100	200
	6 mA	50	100
	8 mA	50	100
	12 mA	25	50
	16 mA	20	40
	24 mA	11	22
1.8V LVCMOS	2 mA	200	225
	4 mA	100	112
	6 mA	50	56
	8 mA	50	56
	12 mA	20	22
	16 mA	20	22
1.5V LVCMOS	2 mA	200	224
	4 mA	100	112
	6 mA	67	75
	8 mA	33	37
	12 mA	33	37
3.3V PCI/PCI-X	Per PCI/PCI-X specification	25	75

Note:

These maximum values are provided for information only. Minimum output buffer resistance values depend on VCCxxxxIOBx, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Microchip website.
R_{(PULL-DOWN-MAX)} = (VOLspec) / IOLspec
R_{(PULL-UP-MAX)} = (VCCImax – VOHspec) / IOHspec

Table 2-28. I/O Output Buffer Maximum Resistances¹—Applicable to MSS I/O Banks
Standard	Drive Strength	RPULL-DOWN (Ω)²	RPULL-UP (Ω)³
3.3V LVTTL / 3.3V LVCMOS	8 mA	50	150
2.5V LVCMOS	8 mA	50	100
1.8V LVCMOS	4 mA	100	112
1.5V LVCMOS	2 mA	200	224

Note:

These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCxxxxIOBx, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Microchip website.
R_{(PULL-DOWN-MAX)} = (VOLspec) / IOLspec
R_{(PULL-UP-MAX)} = (VCCImax – VOHspec) / IOHspec

Table 2-29. I/O Weak Pull-Up/Pull-Down Resistances Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values
VCCxxxxIOBx	R(WEAK PULL-UP)¹ (Ω)		R(WEAK PULL-DOWN)² (Ω)
VCCxxxxIOBx	Min.	Max.	Min.	Max.
3.3V	10k	90k	10k	90k
2.5V	11k	100k	12k	105k
1.8V	18k	110k	17k	150k
1.5V	19k	150k	19k	180k

Note:

R_{(WEAK PULL-DOWN-MAX)} = (VOLspec) / I_{(WEAK PULL-DOWN-MIN)}
R_{(WEAK PULL-UP-MAX)} = (VCCImax – VOHspec) / I_{(WEAK PULL-UP-MIN)}

Table 2-30. I/O Short Currents IOSH/IOSL Applicable to FPGA I/O Banks
	Drive Strength	IOSL (mA)¹	IOSH (mA)¹
3.3V LVTTL/3.3V LVCMOS	2 mA	27	25
	4 mA	27	25
	6 mA	54	51
	8 mA	54	51
	12 mA	109	103
	16 mA	127	132
	24 mA	181	268
2.5V LVCMOS	2 mA	18	16
	4 mA	18	16
	6 mA	37	32
	8 mA	37	32
	12 mA	74	65
	16 mA	87	83
	24 mA	124	169
1.8V LVCMOS	2 mA	11	9
	4 mA	22	17
	6 mA	44	35
	8 mA	51	45
	12 mA	74	91
	16 mA	74	91
1.5V LVCMOS	2 mA	16	13
	4 mA	33	25
	6 mA	39	32
	8 mA	55	66
	12 mA	55	66
3.3V PCI/PCI-X	Per PCI/PCI-X specification	109	103

Note:

T_J = 100 °C.

Table 2-31. I/O Short Currents IOSH/IOSL Applicable to MSS I/O Banks
	Drive Strength	IOSL (mA)¹	IOSH (mA)¹
3.3V LVTTL / 3.3V LVCMOS	8 mA	54	51
2.5V LVCMOS	8 mA	37	32
1.8V LVCMOS	4 mA	22	17
1.5V LVCMOS	2 mA	16	13

Note:

T_J = 100 °C

The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The reliability data below is based on a 3.3V, 12 mA I/O setting, which is the worst case for this type of analysis.

For example, at 100°C, the short current condition would have to be sustained for more than 2200 operation hours to cause a reliability concern. The I/O design does not contain any short circuit protection, but such protection would only be needed in extremely prolonged stress conditions.

Table 2-32. Duration of Short Circuit Event before Failure
Temperature	Time before Failure
–40 °C	> 20 years
0 °C	> 20 years
25 °C	> 20 years
70 °C	5 years
85 °C	2 years
100 °C	6 months
125 °C	1 month

Table 2-33. Schmitt Trigger Input Hysteresis—Hysteresis Voltage Value (typical) for Schmitt Mode Input Buffers
Input Buffer Configuration	Hysteresis Value (typical)
3.3V LVTTL / LVCMOS / PCI / PCI-X (Schmitt trigger mode)	240 mV
2.5V LVCMOS (Schmitt trigger mode)	140 mV
1.8V LVCMOS (Schmitt trigger mode)	80 mV
1.5V LVCMOS (Schmitt trigger mode)	60 mV

Table 2-34. I/O Input Rise Time, Fall Time, and Related I/O Reliability
Input Buffer	Input Rise/Fall Time (min.)	Input Rise/Fall Time (max.)	Reliability
LVTTL/LVCMOS	No requirement	10 ns¹	20 years (110 °C)
LVDS/B-LVDS/ M-LVDS/LVPECL	No requirement	10 ns¹	10 years (100 °C)

Note:

The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the noise is low, then the rise time and fall time of input buffers can be increased beyond the maximum value. The longer the rise/fall times, the more susceptible the input signal is to the board noise. Microchip SoC Products Group recommends signal integrity evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals.