2.3.2.2 Summary of I/O Timing Characteristics—Default I/O Software Settings

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Table 2-22. Summary of AC Measuring Points Applicable to All I/O Bank Types
Standard	Measuring Trip Point (V_trip)
3.3V LVTTL/3.3V LVCMOS	1.4V
2.5V LVCMOS	1.2V
1.8V LVCMOS	0.90V
1.5V LVCMOS	0.75V
3.3V PCI	0.285 × VCCxxxxIOBx (RR)
3.3V PCI	0.615 × VCCxxxxIOBx (FF)
3.3V PCI-X	0.285 × VCCxxxxIOBx (RR)
3.3V PCI-X	0.615 × VCCxxxxIOBx (FF)
LVDS	Cross point
LVPECL	Cross point

Table 2-23. I/O AC Parameter Definitions
Parameter	Parameter Definition
t_DP	Data to pad delay through the output buffer
t_PY	Pad to data delay through the input buffer
t_DOUT	Data to output buffer delay through the I/O interface
t_EOUT	Enable to output buffer tristate control delay through the I/O interface
t_DIN	Input buffer to data delay through the I/O interface
t_HZ	Enable to pad delay through the output buffer—High to Z
t_ZH	Enable to pad delay through the output buffer—Z to High
t_LZ	Enable to pad delay through the output buffer—Low to Z
t_ZL	Enable to pad delay through the output buffer—Z to Low
t_ZHS	Enable to pad delay through the output buffer with delayed enable—Z to High
t_ZLS	Enable to pad delay through the output buffer with delayed enable—Z to Low

Table 2-24. Summary of I/O Timing Characteristics—Software Default Settings–1 Speed Grade, Worst Military-Case Conditions: T_J = 125 °C, Worst Case VCC = 1.425V, Worst-Case VCCxxxxIOBx (per standard) Applicable to FPGA I/O Banks, Assigned to EMC I/O Pins
I/O Standard	Drive Strength	Slew Rate	Capacitive Load (pF)	External Resistor (Ω)	t_DOUT (ns)	t_DP(ns)	t_DIN (ns)	t_PY (ns)	t_EOUT (ns)	t_ZL (ns)	t_ZH (ns)	t_LZ (ns)	t_HZ (ns)	t_ZLS (ns)	t_ZHS (ns)	Units
3.3V LVTTL / 3.3V LVCMOS	12 mA	High	35	—	0.52	3.01	0.03	0.86	0.34	3.06	2.39	2.74	3.02	4.90	4.22	ns
2.5V LVCMOS	12 mA	High	35	—	0.52	3.03	0.03	1.10	0.34	3.09	2.88	2.81	2.90	4.93	4.72	ns
1.8V LVCMOS	12 mA	High	35	—	0.52	3.01	0.03	1.02	0.34	3.07	2.55	3.12	3.41	4.91	4.39	ns
1.5V LVCMOS	12 mA	High	35	—	0.52	3.47	0.03	1.20	0.34	3.54	2.98	3.32	3.50	5.37	4.82	ns
3.3V PCI	Per PCI spec	High	10	25¹	0.52	2.26	0.03	0.73	0.34	2.30	1.68	2.73	3.02	4.14	3.52	ns
3.3V PCI-X	Per PCI-X spec	High	10	25¹	0.52	2.26	0.03	0.69	0.34	2.30	1.68	2.73	3.02	4.14	3.52	ns
LVDS	24 mA	High	—	—	0.52	1.63	0.03	1.36	—	—	—	—	—	—	—	ns
LVPECL	24 mA	High	—	—	0.52	1.57	0.03	1.15	—	—	—	—	—	—	—	ns

Note:

Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-20 for connectivity. This resistor is not required during normal operation.
For specific junction temperature and voltage supply levels, refer to Table 2-7 for derating values.

Table 2-25. Summary of I/O Timing Characteristics—Software Default Settings –1 Speed Grade, Worst Military-Case Conditions: T_J = 125 °C, Worst Case VCC = 1.425V, Worst-Case VCCxxxxIOBx (per standard) Applicable to MSS I/O Banks
I/O Standard	Drive Strength	Slew Rate	Capacitive Load (pF)	External Resistor	t_DOUT (ns)	t_DP (ns)	t_DIN (ns)	t_PY (ns)	t_PYS (ns)	t_EOUT (ns)	t_ZL (ns)	t_ZH (ns)	t_LZ (ns)	t_HZ (ns)	Units
3.3V LVTTL / 3.3V LVCMOS	8 mA	High	10	—	0.19	2.06	0.08	0.84	1.16	0.19	2.10	1.66	1.96	2.19	ns
2.5V LVCMOS	8 mA	High	10	—	0.19	2.10	0.08	1.06	1.24	0.19	2.14	1.95	1.95	2.07	ns
1.8V LVCMOS	4 mA	High	10	—	0.19	2.47	0.08	0.98	1.46	0.19	2.52	2.43	1.97	2.00	ns
1.5V LVCMOS	2 mA	High	10	—	0.19	2.89	0.08	1.14	1.66	0.19	2.94	2.86	2.00	1.98	ns

Note:

Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-20 for connectivity. This resistor is not required during normal operation.
For specific junction temperature and voltage supply levels, refer to Table 2-7 for derating values.

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