2.4.2.1 Timing Characteristics

Table 2-80. Register Delays Worst Military-Case Conditions: T_J = 125 °C, Worst-Case VCC = 1.425V
Parameter	Description	–1	Std.	Units
t_CLKQ	Clock-to-Q of the Core Register	0.58	0.70	ns
t_SUD	Data Setup Time for the Core Register	0.45	0.54	ns
t_HD	Data Hold Time for the Core Register	0.00	0.00	ns
t_SUE	Enable Setup Time for the Core Register	0.48	0.58	ns
t_HE	Enable Hold Time for the Core Register	0.00	0.00	ns
t_CLR2Q	Asynchronous Clear-to-Q of the Core Register	0.42	0.51	ns
t_PRE2Q	Asynchronous Preset-to-Q of the Core Register	0.42	0.51	ns
t_REMCLR	Asynchronous Clear Removal Time for the Core Register	0.00	0.00	ns
t_RECCLR	Asynchronous Clear Recovery Time for the Core Register	0.24	0.28	ns
t_REMPRE	Asynchronous Preset Removal Time for the Core Register	0.00	0.00	ns
t_RECPRE	Asynchronous Preset Recovery Time for the Core Register	0.24	0.28	ns
t_WCLR	Asynchronous Clear Minimum Pulse Width for the Core Register	0.22	0.26	ns
t_WPRE	Asynchronous Preset Minimum Pulse Width for the Core Register	0.22	0.26	ns
t_CKMPWH	Clock Minimum Pulse Width High for the Core Register	0.32	0.38	ns
t_CKMPWL	Clock Minimum Pulse Width Low for the Core Register	0.36	0.42	ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 for derating values.