23.20.1 Host Clock Switching Timings

The following tables, Clock Switching Timings (Worst Case) and Clock Switching Timings Between Two PLLs (Worst Case), provide the worst case timings required for MAIN_CLK to switch from one selected clock to another one. This is in the event that the prescaler is deactivated. When the prescaler is activated, an additional time of 64 clock cycles of the newly selected clock has to be added.

Table 23-3. Clock Switching Timings (Worst Case)
FromMAINCKSLOW_CLKPLL Clock
To
MAINCK–4 x SLOW_CLK +
2.5 x MAINCK3 x PLL Clock +

4 x SLOW_CLK +
1 x MAINCK

SLOW_CLK0.5 x MAINCK + 
4.5 x SLOW_CLK–3 x PLL Clock +
5 x SLOW_CLK
PLL Clock0.5 x MAINCK +
4 x SLOW_CLK +
PLLCOUNT x SLOW_CLK +
2.5 x PLL Clock2.5 x PLL Clock +
5 x SLOW_CLK +
PLLCOUNT x SLOW_CLKSee the following table.
Note:
  1. PLL designates any available PLL of the Clock Generator.
  2. PLLCOUNT designates either PLLACOUNT or UPLLCOUNT.
Table 23-4. Clock Switching Timings Between Two PLLs (Worst Case)
FromPLLA_CLKUPLL Clock
To
PLLA_CLK–3 x PLLA_CLK +
4 x SLOW_CLK +
1.5 x PLLA_CLK
UPLL_CLK_DIV3 x UPLL_CLK_DIV +
4 x SLOW_CLK +
1.5 x UPLL_CLK_DIV–