28.5.4 Slave Mode 10-bit Address Reception

This section describes a standard sequence of events for the MSSP module configured as an I2C slave in 10-bit Addressing mode.

Figure 28-20 is used as a visual reference for this description.

This is a step-by-step process of what must be done by the slave software to accomplish I2C communication.

  1. Bus starts Idle.
  2. Master sends Start condition; S bit is set; SSPxIF is set if interrupt on Start detect is enabled.
  3. Master sends matching high address with R/W bit clear; UA bit is set.
  4. Slave sends ACK and SSPxIF is set.
  5. Software clears the SSPxIF bit.
  6. Software reads received address from SSPxBUF clearing the BF flag.
  7. Slave loads low address into SSPxADD, releasing SCL.
  8. Master sends matching low address byte to the slave; UA bit is set.
    Important: Updates to the SSPxADD register are not allowed until after the ACK sequence.
  9. Slave sends ACK and SSPxIF is set.
    Important: If the low address does not match, SSPxIF and UA are still set so that the slave software can set SSPxADD back to the high address. BF is not set because there is no match. CKP is unaffected.
  10. Slave clears SSPxIF.
  11. Slave reads the received matching address from SSPxBUF clearing BF.
  12. Slave loads high address into SSPxADD.
  13. Master clocks a data byte to the slave and clocks out the slaves ACK on the ninth SCL pulse; SSPxIF is set.
  14. If SEN bit is set, CKP is cleared by hardware and the clock is stretched.
  15. Slave clears SSPxIF.
  16. Slave reads the received byte from SSPxBUF clearing BF.
  17. If SEN is set the slave sets CKP to release the SCL.
  18. Steps 13-17 repeat for each received byte.
  19. Master sends Stop to end the transmission.