33.7.1 ADCON0

ADC Control Register 0
Name: ADCON0
Address: 0xF5B

Bit 76543210 
 ADONADCONT ADCS ADFM ADGO 
Access R/WR/WR/WR/WR/W/HC 
Reset 00000 

Bit 7 – ADON ADC Enable bit

ValueDescription
1 ADC is enabled
0 ADC is disabled

Bit 6 – ADCONT ADC Continuous Operation Enable bit

ValueDescription
1 ADGO is retriggered upon completion of each conversion trigger until ADTIF is set (if ADSOI is set) or until ADGO is cleared (regardless of the value of ADSOI)
0 ADC is cleared upon completion of each conversion trigger

Bit 4 – ADCS ADC Clock Selection bit

ValueDescription
1 Clock supplied from FRC dedicated oscillator
0 Clock supplied by Fosc, divided according to ADCLK register

Bit 2 – ADFM ADC results Format/alignment Selection

ValueDescription
1 ADRES and ADPREV data are right justified
0 ADRES and ADPREV data are left justified, zero-filled

Bit 0 – ADGO ADC Conversion Status bit

ValueDescription
1 ADC conversion cycle in progress. Setting this bit starts an ADC conversion cycle. The bit is cleared by hardware as determined by the ADCONT bit
0 ADC conversion completed/not in progress